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The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER (powernv) processors that keeps a time of day clock. In particular for this model are facilities that initialise and start the time of day clock, and that synchronise that clock to cores on the chip, and to other chips. In this way, all cores on all chips can synchronise timebase (TB). This model implements functionality sufficient to run the skiboot chiptod synchronisation procedure (with the following core timebase state machine implementation). It does not modify the TB in the cores where the real hardware would, because the QEMU ppc timebase implementation is always synchronised acros all cores. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of some CHIPTOD behaviour
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*
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* Copyright (c) 2022-2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PPC_PNV_CHIPTOD_H
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#define PPC_PNV_CHIPTOD_H
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#include "qom/object.h"
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#define TYPE_PNV_CHIPTOD "pnv-chiptod"
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OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD)
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#define TYPE_PNV9_CHIPTOD TYPE_PNV_CHIPTOD "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD)
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#define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD)
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enum tod_state {
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tod_error = 0,
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tod_not_set = 7,
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tod_running = 2,
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tod_stopped = 1,
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};
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struct PnvChipTOD {
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DeviceState xd;
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PnvChip *chip;
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MemoryRegion xscom_regs;
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bool primary;
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bool secondary;
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enum tod_state tod_state;
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uint64_t tod_error;
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uint64_t pss_mss_ctrl_reg;
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};
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struct PnvChipTODClass {
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DeviceClass parent_class;
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void (*broadcast_ttype)(PnvChipTOD *sender, uint32_t trigger);
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int xscom_size;
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};
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#endif /* PPC_PNV_CHIPTOD_H */
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