Richard Henderson c9290dfebf tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs ... TCG register spill/fill uses tcg_out_ld/st with all types, not necessarily going through INDEX_op_{ld,st}_vec. Cc: qemu-stable@nongnu.org Fixes: 16288ded94 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn>		2024-05-15 08:57:39 +02:00
..
tcg-insn-defs.c.inc	tcg/loongarch64: Import LSX instructions	2023-09-15 05:26:50 -07:00
tcg-target-con-set.h	tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128	2023-11-06 08:27:21 -08:00
tcg-target-con-str.h	tcg/loongarch64: Lower add/sub_vec to vadd/vsub	2023-09-15 05:26:51 -07:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs	2024-05-15 08:57:39 +02:00
tcg-target.h	tcg: Introduce TCG_TARGET_HAS_tst	2024-02-03 23:43:48 +00:00
tcg-target.opc.h	tcg/loongarch64: Lower basic tcg vec ops to LSX	2023-09-15 05:26:50 -07:00