qemu/target
Paolo Savini 9425790ace target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.
This patch replaces the use of a helper function with direct tcg ops generation
in order to emulate whole register loads and stores. This is done in order to
improve the performance of QEMU.
We still use the helper function when vstart is not 0 at the beginning of the
emulation of the whole register load or store or when we would end up generating
partial loads or stores of vector elements (e.g. emulating 64 bits element loads
with pairs of 32 bits loads on hosts with 32 bits registers).
The latter condition ensures that we are not surprised by a trap in mid-element
and consecutively that we can update vstart correctly.
We also use the helper function when it performs better than tcg for specific
combinations of vector length, number of fields and element size.

Signed-off-by: Paolo Savini <paolo.savini@embecosm.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Handerson <richard.henderson@linaro.org>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: "Alex Bennée" <alex.bennee@linaro.org>
Message-ID: <20250313152330.398396-2-paolo.savini@embecosm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-05-19 13:30:24 +10:00
..
alpha target/migration: Inline VMSTATE_CPU() 2025-05-08 14:22:12 +02:00
arm target/arm/tcg/vfp_helper: compile file twice (system, user) 2025-05-14 15:12:41 +01:00
avr accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa target/migration: Inline VMSTATE_CPU() 2025-05-08 14:22:12 +02:00
i386 target/i386: Make ITS_NO available to guests 2025-05-12 21:02:51 +02:00
loongarch accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
m68k accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
microblaze target/microblaze: Delay gdb_register_coprocessor() to realize 2025-05-14 14:29:45 +01:00
mips accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
openrisc target/migration: Inline VMSTATE_CPU() 2025-05-08 14:22:12 +02:00
ppc * ci: enable RISC-V cross jobs 2025-05-07 16:10:59 -04:00
riscv target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores. 2025-05-19 13:30:24 +10:00
rx accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
s390x hw/s390x/s390-virtio-ccw: Remove the deprecated 4.0 machine type 2025-05-14 06:58:47 +02:00
sh4 accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
sparc accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
tricore accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
xtensa accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00