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https://github.com/Motorhead1991/qemu.git
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9055ffd76e
microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inconsistent information regarding JALX32 instruction - it is written in the doc that: "To execute a procedure call within the current 256 MB-aligned region (...) The low 26 bits of the target address is the target field shifted left 2 bits." But the target address is already 26 bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
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| .. | ||
| sysemu | ||
| dsp_helper.c | ||
| exception.c | ||
| fpu_helper.c | ||
| ldst_helper.c | ||
| lmmi_helper.c | ||
| meson.build | ||
| micromips_translate.c.inc | ||
| mips16e_translate.c.inc | ||
| msa.decode | ||
| msa_helper.c | ||
| msa_helper.h.inc | ||
| msa_translate.c | ||
| mxu_translate.c | ||
| nanomips_translate.c.inc | ||
| octeon.decode | ||
| octeon_translate.c | ||
| op_helper.c | ||
| rel6.decode | ||
| rel6_translate.c | ||
| sysemu_helper.h.inc | ||
| tcg-internal.h | ||
| trace-events | ||
| trace.h | ||
| translate.c | ||
| translate.h | ||
| translate_addr_const.c | ||
| tx79.decode | ||
| tx79_translate.c | ||
| txx9_translate.c | ||
| vr54xx.decode | ||
| vr54xx_helper.c | ||
| vr54xx_helper.h.inc | ||
| vr54xx_translate.c | ||