Alexander Graf ff871d0462 hw/pci-host/gpex: Allow more than 4 legacy IRQs ... Some boards such as vmapple don't do real legacy PCI IRQ swizzling. Instead, they just keep allocating more board IRQ lines for each new legacy IRQ. Let's support that mode by giving instantiators a new "nr_irqs" property they can use to support more than 4 legacy IRQ lines. In this mode, GPEX will export more IRQ lines, one for each device. Signed-off-by: Alexander Graf <graf@amazon.com> Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241223221645.29911-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2024-12-30 20:04:50 +01:00
..
bootparam.h	hw/xtensa: Include missing 'exec/tswap.h' header	2024-12-14 00:16:20 +01:00
Kconfig	hw/char: Extract serial-mm	2024-10-03 19:33:23 +02:00
meson.build	meson: convert hw/arch*	2020-08-21 06:30:33 -04:00
mx_pic.c	hw/xtensa: fix reset value of MIROUT register of MX PIC	2022-05-06 15:27:40 -07:00
pic_cpu.c	target/xtensa: Include missing 'qemu/atomic.h' header	2023-08-31 19:47:43 +02:00
sim.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
virt.c	hw/pci-host/gpex: Allow more than 4 legacy IRQs	2024-12-30 20:04:50 +01:00
xtensa_memory.c	Do not include cpu.h if it's not really necessary	2021-05-02 17:24:51 +02:00
xtensa_memory.h	Include exec/memory.h slightly less	2019-08-16 13:31:52 +02:00
xtensa_sim.h	hw/xtensa: add virt machine	2019-10-18 20:38:10 -07:00
xtfpga.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00