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* rust: second part of QOM rework * rust: callbacks wrapper * rust: pl011 bugfixes * kvm: cleanup errors in kvm_convert_memory() -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdkaEkUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroN0/wgAgIJg8BrlRKfmiz14NZfph8/jarSj TOWYVxL2v4q98KBuL5pta2ucObgzwqyqSyc02S2DGSOIMQCIiBB5MaCk1iMjx+BO pmVU8gNlD8faO8SSmnnr+jDQt+G+bQ/nRgQJOAReF8oVw3O2aC/FaVKpitMzWtvv PLnJWdrqqpGq14OzX8iNCzSujxppAuyjrhT4lNlekzDoDfdTez72r+rXkvg4GzZL QC3xLYg/LrT8Rs+zgOhm/AaIyS4bOyMlkU9Du1rQ6Tyne45ey2FCwKVzBKrJdGcw sVbzEclxseLenoTbZqYK6JTzLdDoThVUbY2JwoCGUaIm+74P4NjEsUsTVg== =TuQM -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * qdev: second part of Property cleanups * rust: second part of QOM rework * rust: callbacks wrapper * rust: pl011 bugfixes * kvm: cleanup errors in kvm_convert_memory() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdkaEkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroN0/wgAgIJg8BrlRKfmiz14NZfph8/jarSj # TOWYVxL2v4q98KBuL5pta2ucObgzwqyqSyc02S2DGSOIMQCIiBB5MaCk1iMjx+BO # pmVU8gNlD8faO8SSmnnr+jDQt+G+bQ/nRgQJOAReF8oVw3O2aC/FaVKpitMzWtvv # PLnJWdrqqpGq14OzX8iNCzSujxppAuyjrhT4lNlekzDoDfdTez72r+rXkvg4GzZL # QC3xLYg/LrT8Rs+zgOhm/AaIyS4bOyMlkU9Du1rQ6Tyne45ey2FCwKVzBKrJdGcw # sVbzEclxseLenoTbZqYK6JTzLdDoThVUbY2JwoCGUaIm+74P4NjEsUsTVg== # =TuQM # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 13:39:05 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (42 commits) rust: pl011: simplify handling of the FIFO enabled bit in LCR rust: pl011: fix migration stream rust: pl011: extend registers to 32 bits rust: pl011: fix break errors and definition of Data struct rust: pl011: always use reset() method on registers rust: pl011: match break logic of C version rust: pl011: fix declaration of LineControl bits target/i386: Reset TSCs of parked vCPUs too on VM reset kvm: consistently return 0/-errno from kvm_convert_memory rust: qemu-api: add a module to wrap functions and zero-sized closures rust: qom: add initial subset of methods on Object rust: qom: add casting functionality rust: tests: allow writing more than one test bql: add a "mock" BQL for Rust unit tests rust: re-export C types from qemu-api submodules rust: rename qemu-api modules to follow C code a bit more rust: qom: add possibility of overriding unparent rust: qom: put class_init together from multiple ClassInitImpl<> Constify all opaque Property pointers hw/core/qdev-properties: Constify Property argument to PropertyInfo.print ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU Loongson 7A1000 I/O interrupt controller.
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* Copyright (C) 2024 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/intc/loongarch_pic_common.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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static int loongarch_pic_pre_save(void *opaque)
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{
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LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
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LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
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if (lpcc->pre_save) {
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return lpcc->pre_save(s);
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}
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return 0;
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}
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static int loongarch_pic_post_load(void *opaque, int version_id)
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{
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LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
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LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
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if (lpcc->post_load) {
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return lpcc->post_load(s, version_id);
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}
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return 0;
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}
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static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
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{
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LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
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if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
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error_setg(errp, "Invalid 'pic_irq_num'");
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return;
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}
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}
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static const Property loongarch_pic_common_properties[] = {
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DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
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};
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static const VMStateDescription vmstate_loongarch_pic_common = {
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.name = "loongarch_pch_pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = loongarch_pic_pre_save,
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.post_load = loongarch_pic_post_load,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
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VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
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VMSTATE_UINT64(intedge, LoongArchPICCommonState),
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VMSTATE_UINT64(intclr, LoongArchPICCommonState),
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VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
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VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
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VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
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VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
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VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
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VMSTATE_UINT64(intirr, LoongArchPICCommonState),
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VMSTATE_UINT64(intisr, LoongArchPICCommonState),
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VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
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device_class_set_parent_realize(dc, loongarch_pic_common_realize,
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&lpcc->parent_realize);
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device_class_set_props(dc, loongarch_pic_common_properties);
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dc->vmsd = &vmstate_loongarch_pic_common;
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}
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static const TypeInfo loongarch_pic_common_types[] = {
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{
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.name = TYPE_LOONGARCH_PIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LoongArchPICCommonState),
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.class_size = sizeof(LoongArchPICCommonClass),
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.class_init = loongarch_pic_common_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(loongarch_pic_common_types)
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