qemu/hw/ide/isa.c
Stefan Hajnoczi 65cb7129f4 Accel & Exec patch queue
- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
 - Add '-d invalid_mem' logging option (Zoltan)
 - Create QOM containers explicitly (Peter)
 - Rename sysemu/ -> system/ (Philippe)
 - Re-orderning of include/exec/ headers (Philippe)
   Move a lot of declarations from these legacy mixed bag headers:
     . "exec/cpu-all.h"
     . "exec/cpu-common.h"
     . "exec/cpu-defs.h"
     . "exec/exec-all.h"
     . "exec/translate-all"
   to these more specific ones:
     . "exec/page-protection.h"
     . "exec/translation-block.h"
     . "user/cpu_loop.h"
     . "user/guest-host.h"
     . "user/page-protection.h"
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Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging

Accel & Exec patch queue

- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
- Add '-d invalid_mem' logging option (Zoltan)
- Create QOM containers explicitly (Peter)
- Rename sysemu/ -> system/ (Philippe)
- Re-orderning of include/exec/ headers (Philippe)
  Move a lot of declarations from these legacy mixed bag headers:
    . "exec/cpu-all.h"
    . "exec/cpu-common.h"
    . "exec/cpu-defs.h"
    . "exec/exec-all.h"
    . "exec/translate-all"
  to these more specific ones:
    . "exec/page-protection.h"
    . "exec/translation-block.h"
    . "user/cpu_loop.h"
    . "user/guest-host.h"
    . "user/page-protection.h"

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 # gpg: WARNING: This key is not certified with a trusted signature!
 # gpg:          There is no indication that the signature belongs to the owner.
 # Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits)
  util/qemu-timer: fix indentation
  meson: Do not define CONFIG_DEVICES on user emulation
  system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header
  system/numa: Remove unnecessary 'exec/cpu-common.h' header
  hw/xen: Remove unnecessary 'exec/cpu-common.h' header
  target/mips: Drop left-over comment about Jazz machine
  target/mips: Remove tswap() calls in semihosting uhi_fstat_cb()
  target/xtensa: Remove tswap() calls in semihosting simcall() helper
  accel/tcg: Un-inline translator_is_same_page()
  accel/tcg: Include missing 'exec/translation-block.h' header
  accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'
  accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h'
  qemu/coroutine: Include missing 'qemu/atomic.h' header
  exec/translation-block: Include missing 'qemu/atomic.h' header
  accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h'
  exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined
  target/sparc: Move sparc_restore_state_to_opc() to cpu.c
  target/sparc: Uninline cpu_get_tb_cpu_state()
  target/loongarch: Declare loongarch_cpu_dump_state() locally
  user: Move various declarations out of 'exec/exec-all.h'
  ...

Conflicts:
	hw/char/riscv_htif.c
	hw/intc/riscv_aplic.c
	target/s390x/cpu.c

	Apply sysemu header path changes to not in the pull request.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21 11:07:00 -05:00

133 lines
4 KiB
C

/*
* QEMU IDE Emulation: ISA Bus support.
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2006 Openedhand Ltd.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "system/dma.h"
#include "hw/ide/isa.h"
#include "qom/object.h"
#include "ide-internal.h"
/***********************************************************/
/* ISA IDE definitions */
struct ISAIDEState {
ISADevice parent_obj;
IDEBus bus;
uint32_t iobase;
uint32_t iobase2;
uint32_t irqnum;
};
static void isa_ide_reset(DeviceState *d)
{
ISAIDEState *s = ISA_IDE(d);
ide_bus_reset(&s->bus);
}
static const VMStateDescription vmstate_ide_isa = {
.name = "isa-ide",
.version_id = 3,
.minimum_version_id = 0,
.fields = (const VMStateField[]) {
VMSTATE_IDE_BUS(bus, ISAIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, ISAIDEState),
VMSTATE_END_OF_LIST()
}
};
static void isa_ide_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
ISAIDEState *s = ISA_IDE(dev);
ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
ide_bus_init_output_irq(&s->bus, isa_get_irq(isadev, s->irqnum));
vmstate_register_any(VMSTATE_IF(dev), &vmstate_ide_isa, s);
ide_bus_register_restart_cb(&s->bus);
}
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
DriveInfo *hd0, DriveInfo *hd1)
{
DeviceState *dev;
ISADevice *isadev;
ISAIDEState *s;
isadev = isa_new(TYPE_ISA_IDE);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", iobase);
qdev_prop_set_uint32(dev, "iobase2", iobase2);
qdev_prop_set_uint32(dev, "irq", irqnum);
isa_realize_and_unref(isadev, bus, &error_fatal);
s = ISA_IDE(dev);
if (hd0) {
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1) {
ide_bus_create_drive(&s->bus, 1, hd1);
}
return isadev;
}
static const Property isa_ide_properties[] = {
DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0),
DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
DEFINE_PROP_UINT32("irq", ISAIDEState, irqnum, 14),
};
static void isa_ide_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = isa_ide_realizefn;
dc->fw_name = "ide";
device_class_set_legacy_reset(dc, isa_ide_reset);
device_class_set_props(dc, isa_ide_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static const TypeInfo isa_ide_info = {
.name = TYPE_ISA_IDE,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(ISAIDEState),
.class_init = isa_ide_class_initfn,
};
static void isa_ide_register_types(void)
{
type_register_static(&isa_ide_info);
}
type_init(isa_ide_register_types)