Sai Pavan Boddu 77aad42ee2 hw/riscv: Add Microblaze V generic board ... Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial configuration is going beyond what it is configured by default because validation should be done on other configurations too. That's why wire also additional uart16500, axi ethernet(with axi dma). GPIOs, i2c and qspi is also listed for completeness. IRQ map is: (addr) 0 - timer (0x41c00000) 1 - uartlite (0x40600000) 2 - i2c (0x40800000) 3 - qspi (0x44a00000) 4 - uart16550 (0x44a10000) 5 - emaclite (0x40e00000) 6 - timer2 (0x41c10000) 7 - axi emac (0x40c00000) 8 - axi dma (0x41e00000) 9 - axi dma 10 - gpio (0x40000000) 11 - gpio2 (0x40010000) 12 - gpio3 (0x40020000) Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-12-20 11:22:47 +10:00
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microblaze-v-generic.rst	hw/riscv: Add Microblaze V generic board	2024-12-20 11:22:47 +10:00
microchip-icicle-kit.rst	docs: Format literals correctly	2021-08-02 11:42:38 +01:00
shakti-c.rst	Fix some typos in documentation (found by codespell)	2021-11-22 15:02:38 +01:00
sifive_u.rst	docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions	2024-01-10 18:47:47 +10:00
virt.rst	docs: update riscv/virt.rst with kernel-irqchip=split support	2024-12-20 11:22:47 +10:00