qemu/hw/cxl
Li Zhijian 8f90a54cfa hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector
assignments specific to the Type 3 (T3) CXL device.

The primary goal of this change is to encapsulate the MSIX vector uses
that are unique to the T3 device within an enumeration, improving code
readability and maintenance by avoiding magic numbers. This organizational
change allows for more explicit references to each vector’s role, thereby
reducing the potential for misconfiguration.

It also modified `mailbox_reg_init_common` to accept the `msi_n` parameter,
reflecting the new MSIX vector setup.

This pertains to the T3 device privately; other endpoints should refrain from
using it, despite its public accessibility to all of them.

Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20250203161908.145406-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-21 07:18:42 -05:00
..
cxl-cdat.c hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean 2024-04-25 12:48:12 +02:00
cxl-component-utils.c hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge. 2024-03-12 17:56:55 -04:00
cxl-device-utils.c hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration 2025-02-21 07:18:42 -05:00
cxl-events.c hw/cxl/events: discard all event records during sanitation 2024-07-21 14:31:59 -04:00
cxl-host-stubs.c pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. 2022-06-09 19:32:49 -04:00
cxl-host.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
cxl-mailbox-utils.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
Kconfig hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) 2022-05-13 06:13:35 -04:00
meson.build meson: remove CONFIG_ALL 2023-12-31 09:11:28 +01:00
switch-mailbox-cci.c hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration 2025-02-21 07:18:42 -05:00