qemu/target
Richard Henderson 8a40fe5f1b target/arm: Rearrange {sve,fp}_check_access assert
We want to ensure that access is checked by the time we ask
for a specific fp/vector register.  We want to ensure that
we do not emit two lots of code to raise an exception.

But sometimes it's difficult to cleanly organize the code
such that we never pass through sve_check_access exactly once.
Allow multiple calls so long as the result is true, that is,
no exception to be raised.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-28 10:02:47 +01:00
..
alpha meson: target 2020-08-21 06:30:35 -04:00
arm target/arm: Rearrange {sve,fp}_check_access assert 2020-08-28 10:02:47 +01:00
avr meson: target 2020-08-21 06:30:35 -04:00
cris meson: target 2020-08-21 06:30:35 -04:00
hppa meson: target 2020-08-21 06:30:35 -04:00
i386 meson: target 2020-08-21 06:30:35 -04:00
lm32 meson: target 2020-08-21 06:30:35 -04:00
m68k meson: target 2020-08-21 06:30:35 -04:00
microblaze target/microblaze: mbar: Trap sleeps from user-space 2020-08-24 10:47:27 +02:00
mips meson: target 2020-08-21 06:30:35 -04:00
moxie meson: target 2020-08-21 06:30:35 -04:00
nios2 meson: target 2020-08-21 06:30:35 -04:00
openrisc meson: target 2020-08-21 06:30:35 -04:00
ppc ppc patch queue 2020-08-18 2020-08-24 09:35:21 +01:00
riscv target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
rx meson: target 2020-08-21 06:30:35 -04:00
s390x target/s390x: fix meson.build issue 2020-08-21 11:55:13 -04:00
sh4 meson: target 2020-08-21 06:30:35 -04:00
sparc meson: target 2020-08-21 06:30:35 -04:00
tilegx meson: target 2020-08-21 06:30:35 -04:00
tricore meson: target 2020-08-21 06:30:35 -04:00
unicore32 meson: target 2020-08-21 06:30:35 -04:00
xtensa target/xtensa: import DSP3400 core 2020-08-21 12:56:45 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00