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96a2132ce9
Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter. Also added qtests for the same. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
112 lines
4.3 KiB
C
112 lines
4.3 KiB
C
/*
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* QTest testcase for PowerNV 10 interrupt controller (xive2)
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef TEST_PNV_XIVE2_COMMON_H
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#define TEST_PNV_XIVE2_COMMON_H
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#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
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#define PPC_BIT32(bit) (0x80000000 >> (bit))
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#define PPC_BIT8(bit) (0x80 >> (bit))
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#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
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#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
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PPC_BIT32(bs))
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#include "qemu/bswap.h"
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#include "hw/intc/pnv_xive2_regs.h"
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#include "hw/ppc/xive_regs.h"
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#include "hw/ppc/xive2_regs.h"
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/*
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* sizing:
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* 128 interrupts
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* => ESB BAR range: 16M
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* 256 ENDs
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* => END BAR range: 16M
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* 256 VPs
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* => NVPG,NVC BAR range: 32M
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*/
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#define MAX_IRQS 128
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#define MAX_ENDS 256
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#define MAX_VPS 256
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#define XIVE_PAGE_SHIFT 16
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#define XIVE_TRIGGER_PAGE 0
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#define XIVE_EOI_PAGE 1
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#define XIVE_IC_ADDR 0x0006030200000000ull
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#define XIVE_IC_TM_INDIRECT (XIVE_IC_ADDR + (256 << XIVE_PAGE_SHIFT))
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#define XIVE_IC_BAR ((0x3ull << 62) | XIVE_IC_ADDR)
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#define XIVE_TM_BAR 0xc006030203180000ull
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#define XIVE_ESB_ADDR 0x0006050000000000ull
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#define XIVE_ESB_BAR ((0x3ull << 62) | XIVE_ESB_ADDR)
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#define XIVE_END_BAR 0xc006060000000000ull
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#define XIVE_NVPG_ADDR 0x0006040000000000ull
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#define XIVE_NVPG_BAR ((0x3ull << 62) | XIVE_NVPG_ADDR)
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#define XIVE_NVC_ADDR 0x0006030208000000ull
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#define XIVE_NVC_BAR ((0x3ull << 62) | XIVE_NVC_ADDR)
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/*
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* Memory layout
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* A check is done when a table is configured to ensure that the max
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* size of the resource fits in the table.
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*/
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#define XIVE_VST_SIZE 0x10000ull /* must be at least 4k */
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#define XIVE_MEM_START 0x10000000ull
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#define XIVE_ESB_MEM XIVE_MEM_START
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#define XIVE_EAS_MEM (XIVE_ESB_MEM + XIVE_VST_SIZE)
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#define XIVE_END_MEM (XIVE_EAS_MEM + XIVE_VST_SIZE)
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#define XIVE_NVP_MEM (XIVE_END_MEM + XIVE_VST_SIZE)
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#define XIVE_NVG_MEM (XIVE_NVP_MEM + XIVE_VST_SIZE)
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#define XIVE_NVC_MEM (XIVE_NVG_MEM + XIVE_VST_SIZE)
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#define XIVE_SYNC_MEM (XIVE_NVC_MEM + XIVE_VST_SIZE)
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#define XIVE_QUEUE_MEM (XIVE_SYNC_MEM + XIVE_VST_SIZE)
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#define XIVE_QUEUE_SIZE 4096 /* per End */
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#define XIVE_REPORT_MEM (XIVE_QUEUE_MEM + XIVE_QUEUE_SIZE * MAX_VPS)
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#define XIVE_REPORT_SIZE 256 /* two cache lines per NVP */
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#define XIVE_MEM_END (XIVE_REPORT_MEM + XIVE_REPORT_SIZE * MAX_VPS)
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#define P10_XSCOM_BASE 0x000603fc00000000ull
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#define XIVE_XSCOM 0x2010800ull
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#define XIVE_ESB_RESET 0b00
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#define XIVE_ESB_OFF 0b01
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#define XIVE_ESB_PENDING 0b10
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#define XIVE_ESB_QUEUED 0b11
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#define XIVE_ESB_GET 0x800
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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extern uint64_t pnv_xive_xscom_read(QTestState *qts, uint32_t reg);
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extern void pnv_xive_xscom_write(QTestState *qts, uint32_t reg, uint64_t val);
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extern uint64_t xive_get_queue_addr(uint32_t end_index);
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extern uint8_t get_esb(QTestState *qts, uint32_t index, uint8_t page,
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uint32_t offset);
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extern void set_esb(QTestState *qts, uint32_t index, uint8_t page,
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uint32_t offset, uint32_t val);
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extern void get_nvp(QTestState *qts, uint32_t index, Xive2Nvp* nvp);
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extern void set_nvp(QTestState *qts, uint32_t index, uint8_t first);
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extern void get_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair);
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extern void set_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair);
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extern void set_nvg(QTestState *qts, uint32_t index, uint8_t next);
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extern void set_eas(QTestState *qts, uint32_t index, uint32_t end_index,
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uint32_t data);
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extern void set_end(QTestState *qts, uint32_t index, uint32_t nvp_index,
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uint8_t priority, bool i);
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void test_flush_sync_inject(QTestState *qts);
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void test_nvpg_bar(QTestState *qts);
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#endif /* TEST_PNV_XIVE2_COMMON_H */
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