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1016b0364f
While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* T-Head-specific CSRs.
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*
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* Copyright (c) 2024 VRULL GmbH
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu_vendorid.h"
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#define CSR_TH_SXSTATUS 0x5c0
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/* TH_SXSTATUS bits */
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#define TH_SXSTATUS_UCME BIT(16)
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#define TH_SXSTATUS_MAEE BIT(21)
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#define TH_SXSTATUS_THEADISAEE BIT(22)
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static RISCVException smode(CPURISCVState *env, int csrno)
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{
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if (riscv_has_ext(env, RVS)) {
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return RISCV_EXCP_NONE;
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}
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return RISCV_EXCP_ILLEGAL_INST;
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}
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static bool test_thead_mvendorid(RISCVCPU *cpu)
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{
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return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
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}
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static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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/* We don't set MAEE here, because QEMU does not implement MAEE. */
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*val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
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return RISCV_EXCP_NONE;
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}
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const RISCVCSR th_csr_list[] = {
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{
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.csrno = CSR_TH_SXSTATUS,
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.insertion_test = test_thead_mvendorid,
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.csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
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},
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{ }
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};
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