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8201f1a29c
By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
37 lines
876 B
C
37 lines
876 B
C
/*
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* RISC-V cpu parameters for qemu.
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*
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* Copyright (c) 2017-2018 SiFive, Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef RISCV_CPU_PARAM_H
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#define RISCV_CPU_PARAM_H
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#if defined(TARGET_RISCV64)
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# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
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#elif defined(TARGET_RISCV32)
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# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
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#endif
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#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
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/*
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* RISC-V-specific extra insn start words:
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* 1: Original instruction opcode
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* 2: more information about instruction
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*/
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#define TARGET_INSN_START_EXTRA_WORDS 2
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/*
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* The current MMU Modes are:
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* - U mode 0b000
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* - S mode 0b001
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* - M mode 0b011
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* - U mode HLV/HLVX/HSV 0b100
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* - S mode HLV/HLVX/HSV 0b101
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* - M mode HLV/HLVX/HSV 0b111
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*/
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#endif
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