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a59a876999
For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
244 lines
6.3 KiB
C
244 lines
6.3 KiB
C
/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_AVR_CPU_H
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#define QEMU_AVR_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-common.h"
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#include "exec/cpu-defs.h"
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#include "exec/cpu-interrupt.h"
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#include "system/memory.h"
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#ifdef CONFIG_USER_ONLY
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#error "AVR 8-bit does not support user mode"
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#endif
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#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
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/*
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* AVR has two memory spaces, data & code.
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* e.g. both have 0 address
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* ST/LD instructions access data space
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* LPM/SPM and instruction fetching access code memory space
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*/
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#define MMU_CODE_IDX 0
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#define MMU_DATA_IDX 1
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#define EXCP_RESET 1
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#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
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/* Number of CPU registers */
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#define NUMBER_OF_CPU_REGISTERS 32
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/* CPU registers mapped into i/o ports 0x38-0x3f. */
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#define REG_38_RAMPD 0
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#define REG_38_RAMPX 1
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#define REG_38_RAMPY 2
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#define REG_38_RAMPZ 3
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#define REG_38_EIDN 4
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#define REG_38_SPL 5
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#define REG_38_SPH 6
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#define REG_38_SREG 7
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/*
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* Offsets of AVR memory regions in host memory space.
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*
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* This is needed because the AVR has separate code and data address
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* spaces that both have start from zero but have to go somewhere in
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* host memory.
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*
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* It's also useful to know where some things are, like the IO registers.
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*/
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/* Flash program memory */
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#define OFFSET_CODE 0x00000000
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/* CPU registers, IO registers, and SRAM */
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#define OFFSET_DATA 0x00800000
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/*
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* IO registers, including status register, stack pointer, and memory
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* mapped peripherals, mapped just after CPU registers
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*/
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#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
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typedef enum AVRFeature {
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AVR_FEATURE_SRAM,
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AVR_FEATURE_1_BYTE_PC,
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AVR_FEATURE_2_BYTE_PC,
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AVR_FEATURE_3_BYTE_PC,
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AVR_FEATURE_1_BYTE_SP,
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AVR_FEATURE_2_BYTE_SP,
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AVR_FEATURE_BREAK,
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AVR_FEATURE_DES,
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AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */
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AVR_FEATURE_EIJMP_EICALL,
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AVR_FEATURE_IJMP_ICALL,
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AVR_FEATURE_JMP_CALL,
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AVR_FEATURE_ADIW_SBIW,
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AVR_FEATURE_SPM,
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AVR_FEATURE_SPMX,
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AVR_FEATURE_ELPMX,
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AVR_FEATURE_ELPM,
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AVR_FEATURE_LPMX,
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AVR_FEATURE_LPM,
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AVR_FEATURE_MOVW,
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AVR_FEATURE_MUL,
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AVR_FEATURE_RAMPD,
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AVR_FEATURE_RAMPX,
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AVR_FEATURE_RAMPY,
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AVR_FEATURE_RAMPZ,
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} AVRFeature;
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typedef struct CPUArchState {
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uint32_t pc_w; /* 0x003fffff up to 22 bits */
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uint32_t sregC; /* 0x00000001 1 bit */
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uint32_t sregZ; /* 0x00000001 1 bit */
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uint32_t sregN; /* 0x00000001 1 bit */
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uint32_t sregV; /* 0x00000001 1 bit */
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uint32_t sregS; /* 0x00000001 1 bit */
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uint32_t sregH; /* 0x00000001 1 bit */
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uint32_t sregT; /* 0x00000001 1 bit */
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uint32_t sregI; /* 0x00000001 1 bit */
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uint32_t rampD; /* 0x00ff0000 8 bits */
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uint32_t rampX; /* 0x00ff0000 8 bits */
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uint32_t rampY; /* 0x00ff0000 8 bits */
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uint32_t rampZ; /* 0x00ff0000 8 bits */
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uint32_t eind; /* 0x00ff0000 8 bits */
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uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */
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uint32_t sp; /* 16 bits */
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uint32_t skip; /* if set skip instruction */
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uint64_t intsrc; /* interrupt sources */
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bool fullacc; /* CPU/MEM if true MEM only otherwise */
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uint64_t features;
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} CPUAVRState;
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/**
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* AVRCPU:
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* @env: #CPUAVRState
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*
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* A AVR CPU.
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*/
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struct ArchCPU {
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CPUState parent_obj;
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CPUAVRState env;
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MemoryRegion cpu_reg1;
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MemoryRegion cpu_reg2;
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/* Initial value of stack pointer */
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uint32_t init_sp;
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};
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/**
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* AVRCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A AVR CPU model.
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*/
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struct AVRCPUClass {
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CPUClass parent_class;
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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extern const struct VMStateDescription vms_avr_cpu;
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void avr_cpu_do_interrupt(CPUState *cpu);
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bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int avr_print_insn(bfd_vma addr, disassemble_info *info);
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vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
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static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
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{
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return (env->features & (1U << feature)) != 0;
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}
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static inline void set_avr_feature(CPUAVRState *env, int feature)
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{
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env->features |= (1U << feature);
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}
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void avr_cpu_tcg_init(void);
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void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
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int *max_insns, vaddr pc, void *host_pc);
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int cpu_avr_exec(CPUState *cpu);
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enum {
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TB_FLAGS_FULL_ACCESS = 1,
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TB_FLAGS_SKIP = 2,
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};
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static inline int cpu_interrupts_enabled(CPUAVRState *env)
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{
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return env->sregI != 0;
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}
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static inline uint8_t cpu_get_sreg(CPUAVRState *env)
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{
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return (env->sregC) << 0
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| (env->sregZ) << 1
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| (env->sregN) << 2
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| (env->sregV) << 3
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| (env->sregS) << 4
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| (env->sregH) << 5
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| (env->sregT) << 6
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| (env->sregI) << 7;
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}
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static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
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{
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env->sregC = (sreg >> 0) & 0x01;
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env->sregZ = (sreg >> 1) & 0x01;
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env->sregN = (sreg >> 2) & 0x01;
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env->sregV = (sreg >> 3) & 0x01;
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env->sregS = (sreg >> 4) & 0x01;
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env->sregH = (sreg >> 5) & 0x01;
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env->sregT = (sreg >> 6) & 0x01;
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env->sregI = (sreg >> 7) & 0x01;
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}
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bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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extern const MemoryRegionOps avr_cpu_reg1;
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extern const MemoryRegionOps avr_cpu_reg2;
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#endif /* QEMU_AVR_CPU_H */
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