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c1149f69ab
Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
/*
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* QEMU RISC-V Hart Array interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Holds the state of a heterogeneous array of RISC-V harts
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_HART_H
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#define HW_RISCV_HART_H
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "qom/object.h"
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#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_HART_ARRAY)
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struct RISCVHartArrayState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t num_harts;
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uint32_t hartid_base;
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char *cpu_type;
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uint64_t resetvec;
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uint32_t num_rnmi_irqvec;
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uint64_t *rnmi_irqvec;
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uint32_t num_rnmi_excpvec;
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uint64_t *rnmi_excpvec;
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RISCVCPU *harts;
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};
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#endif
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