mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-27 04:13:53 -06:00
fa19fe4e3a
To establish performance characteristics of a CXL device when used via a particular CXL topology (root ports, switches, end points) it is necessary to set the appropriate link speed and width in the PCI Express capability structure. Provide x-speed and x-link properties for this. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
23 lines
404 B
C
23 lines
404 B
C
|
|
#ifndef CXL_USP_H
|
|
#define CXL_USP_H
|
|
#include "hw/pci/pcie.h"
|
|
#include "hw/pci/pcie_port.h"
|
|
#include "hw/cxl/cxl.h"
|
|
|
|
typedef struct CXLUpstreamPort {
|
|
/*< private >*/
|
|
PCIEPort parent_obj;
|
|
|
|
/*< public >*/
|
|
CXLComponentState cxl_cstate;
|
|
CXLCCI swcci;
|
|
|
|
PCIExpLinkSpeed speed;
|
|
PCIExpLinkWidth width;
|
|
|
|
DOECap doe_cdat;
|
|
uint64_t sn;
|
|
} CXLUpstreamPort;
|
|
|
|
#endif /* CXL_SUP_H */
|