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8e002a6931
Currently, it does not support the CRYPT command. Instead, it only sends an interrupt to notify the firmware that the crypt command has completed. It is a temporary workaround to resolve the boot issue in the Crypto Manager Self Test. Introduce a new "use_crypt_workaround" class attribute and set it to true in the AST2700 HACE model to enable this workaround by default for AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
/*
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* ASPEED Hash and Crypto Engine
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*
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* Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates
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* Copyright (C) 2021 IBM Corp.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_HACE_H
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#define ASPEED_HACE_H
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#include "hw/sysbus.h"
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#include "crypto/hash.h"
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#define TYPE_ASPEED_HACE "aspeed.hace"
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#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
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#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
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#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
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#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
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#define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700"
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OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
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#define ASPEED_HACE_NR_REGS (0x64 >> 2)
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#define ASPEED_HACE_MAX_SG 256 /* max number of entries */
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struct AspeedHACEState {
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SysBusDevice parent;
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MemoryRegion iomem;
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qemu_irq irq;
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struct iovec iov_cache[ASPEED_HACE_MAX_SG];
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uint32_t regs[ASPEED_HACE_NR_REGS];
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uint32_t total_req_len;
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uint32_t iov_count;
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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QCryptoHash *hash_ctx;
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};
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struct AspeedHACEClass {
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SysBusDeviceClass parent_class;
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uint32_t src_mask;
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uint32_t dest_mask;
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uint32_t key_mask;
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uint32_t hash_mask;
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bool raise_crypt_interrupt_workaround;
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};
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#endif /* ASPEED_HACE_H */
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