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e0c87e3067
The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode APLIC controller. Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This attribute represents the base configuration address for MSIs, in our case the base addr of the IMSIC controller. This attribute is being set only when running irqchip_split() mode with aia=aplic-imsic. During riscv_aplic_msi_send() we'll check if the attribute was set to skip the check for a m-mode APLIC controller and to change the resulting MSI addr by adding kvm_msicfgaddr right before address_space_stl_le(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/*
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* RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_APLIC_H
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#define HW_RISCV_APLIC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_RISCV_APLIC "riscv.aplic"
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typedef struct RISCVAPLICState RISCVAPLICState;
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DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
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#define APLIC_MIN_SIZE 0x4000
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#define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \
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~(APLIC_MIN_SIZE - 1))
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#define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \
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APLIC_SIZE_ALIGN(32 * (__num_harts)))
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struct RISCVAPLICState {
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/*< private >*/
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SysBusDevice parent_obj;
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qemu_irq *external_irqs;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t bitfield_words;
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uint32_t domaincfg;
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uint32_t mmsicfgaddr;
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uint32_t mmsicfgaddrH;
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uint32_t smsicfgaddr;
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uint32_t smsicfgaddrH;
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uint32_t genmsi;
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uint32_t *sourcecfg;
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uint32_t *state;
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uint32_t *target;
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uint32_t *idelivery;
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uint32_t *iforce;
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uint32_t *ithreshold;
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/* topology */
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#define QEMU_APLIC_MAX_CHILDREN 16
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struct RISCVAPLICState *parent;
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struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
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uint16_t num_children;
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/* config */
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uint32_t aperture_size;
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uint32_t hartid_base;
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uint32_t num_harts;
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uint32_t iprio_mask;
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uint32_t num_irqs;
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bool msimode;
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bool mmode;
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/* To support KVM aia=aplic-imsic with irqchip split mode */
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bool kvm_splitmode;
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uint32_t kvm_msicfgaddr;
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uint32_t kvm_msicfgaddrH;
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};
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void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
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bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
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bool riscv_use_emulated_aplic(bool msimode);
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void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr);
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DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
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uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
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uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
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#endif
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