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c528f10dce
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-tsp
Support TSPINT128 to TSPINT136 in INTC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I3f3aca4b90129640369cf4a92deb4b9a12df5b70
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-5-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* ASPEED INTC Controller
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_INTC_H
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#define ASPEED_INTC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "hw/or-irq.h"
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#define TYPE_ASPEED_INTC "aspeed.intc"
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#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
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#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
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#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
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#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
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#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
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#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
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OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
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#define ASPEED_INTC_MAX_INPINS 10
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#define ASPEED_INTC_MAX_OUTPINS 19
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typedef struct AspeedINTCIRQ {
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int inpin_idx;
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int outpin_idx;
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int num_outpins;
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uint32_t enable_reg;
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uint32_t status_reg;
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} AspeedINTCIRQ;
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struct AspeedINTCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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MemoryRegion iomem_container;
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uint32_t *regs;
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OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
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qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
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uint32_t enable[ASPEED_INTC_MAX_INPINS];
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uint32_t mask[ASPEED_INTC_MAX_INPINS];
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uint32_t pending[ASPEED_INTC_MAX_INPINS];
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};
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struct AspeedINTCClass {
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SysBusDeviceClass parent_class;
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uint32_t num_lines;
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uint32_t num_inpins;
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uint32_t num_outpins;
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uint64_t mem_size;
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uint64_t nr_regs;
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uint64_t reg_offset;
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const MemoryRegionOps *reg_ops;
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const AspeedINTCIRQ *irq_table;
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int irq_table_count;
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};
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#endif /* ASPEED_INTC_H */
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