mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-27 04:13:53 -06:00

- Replace cpu_list() definition by CPUClass::list_cpus() callback - Remove few MO_TE definitions on Hexagon / X86 targets - Remove target_ulong uses in ARMMMUFaultInfo and ARM CPUWatchpoint - Remove DEVICE_HOST_ENDIAN definition - Evaluate TARGET_BIG_ENDIAN at compile time and use target_needs_bswap() more - Rename target_words_bigendian() as target_big_endian() - Convert target_name() and target_cpu_type() to TargetInfo API - Constify QOM TypeInfo class_data/interfaces fields - Get default_cpu_type calling machine_class_default_cpu_type() - Correct various uses of GLibCompareDataFunc prototype - Simplify ARM/Aarch64 gdb_get_core_xml_file() handling a bit - Move device tree files in their own pc-bios/dtb/ subdir - Correctly check strchrnul() symbol availability on macOS SDK - Move target-agnostic methods out of cpu-target.c and accel-target.c - Unmap canceled USB XHCI packet - Use deposit/extract API in designware model - Fix MIPS16e translation - Few missing header fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmgLqb8ACgkQ4+MsLN6t wN6nCQ//cmv1M+NsndhO5TAK8T1eUSXKlTZh932uro6ZgxKwN4p+j1Qo7bq3O9gu qUMHNbcfQl8sHSytiXBoxCjLMCXC3u38iyz75WGXuPay06rs4wqmahqxL4tyno3l 1RviFts9xlLn+tJqqrAR6+pRdALld0TY+yXUjXgr4aK5pIRpLz9U/sIEoh7qbA5U x0MTaceDG3A91OYo0TgrNbcMe1b9GqQZ+a4tbaP+oE37wbiKdyQ68LjrEbV08Y1O qrFF4oxquV31QJcUiuII1W7hC6psGrMsUA1f1qDu7QvmybAZWNZNsR9T66X9jH5J wXMShJmmXwxugohmuPPFnDshzJy90aFL6Jy2shrfqcG2v0W66ARY1ZnbJLCcfczt 073bnE2dnOVhd/ny37RrIJNJLLmYM0yFDeKuYtNNAzpK9fpA7Q2PI8QiqNacQ3Pa TdEYrGlMk7OeNck8xJmJMY5rATthi1D4dIBv3rjQbUolQvPJe2Y9or0R2WL1jK5v hhr6DY01iSPES3CravmUs/aB1HRMPi/nX45OmFR6frAB7xqWMreh81heBVuoTTK8 PuXtRQgRMRKwDeTxlc6p+zba4mIEYG8rqJtPFRgViNCJ1KsgSIowup3BNU05YuFn NoPoRayMDVMgejVgJin3Mg2DCYvt/+MBmO4IoggWlFsXj59uUgA= =DXnZ -----END PGP SIGNATURE----- Merge tag 'single-binary-20250425' of https://github.com/philmd/qemu into staging Various patches loosely related to single binary work: - Replace cpu_list() definition by CPUClass::list_cpus() callback - Remove few MO_TE definitions on Hexagon / X86 targets - Remove target_ulong uses in ARMMMUFaultInfo and ARM CPUWatchpoint - Remove DEVICE_HOST_ENDIAN definition - Evaluate TARGET_BIG_ENDIAN at compile time and use target_needs_bswap() more - Rename target_words_bigendian() as target_big_endian() - Convert target_name() and target_cpu_type() to TargetInfo API - Constify QOM TypeInfo class_data/interfaces fields - Get default_cpu_type calling machine_class_default_cpu_type() - Correct various uses of GLibCompareDataFunc prototype - Simplify ARM/Aarch64 gdb_get_core_xml_file() handling a bit - Move device tree files in their own pc-bios/dtb/ subdir - Correctly check strchrnul() symbol availability on macOS SDK - Move target-agnostic methods out of cpu-target.c and accel-target.c - Unmap canceled USB XHCI packet - Use deposit/extract API in designware model - Fix MIPS16e translation - Few missing header fixes # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmgLqb8ACgkQ4+MsLN6t # wN6nCQ//cmv1M+NsndhO5TAK8T1eUSXKlTZh932uro6ZgxKwN4p+j1Qo7bq3O9gu # qUMHNbcfQl8sHSytiXBoxCjLMCXC3u38iyz75WGXuPay06rs4wqmahqxL4tyno3l # 1RviFts9xlLn+tJqqrAR6+pRdALld0TY+yXUjXgr4aK5pIRpLz9U/sIEoh7qbA5U # x0MTaceDG3A91OYo0TgrNbcMe1b9GqQZ+a4tbaP+oE37wbiKdyQ68LjrEbV08Y1O # qrFF4oxquV31QJcUiuII1W7hC6psGrMsUA1f1qDu7QvmybAZWNZNsR9T66X9jH5J # wXMShJmmXwxugohmuPPFnDshzJy90aFL6Jy2shrfqcG2v0W66ARY1ZnbJLCcfczt # 073bnE2dnOVhd/ny37RrIJNJLLmYM0yFDeKuYtNNAzpK9fpA7Q2PI8QiqNacQ3Pa # TdEYrGlMk7OeNck8xJmJMY5rATthi1D4dIBv3rjQbUolQvPJe2Y9or0R2WL1jK5v # hhr6DY01iSPES3CravmUs/aB1HRMPi/nX45OmFR6frAB7xqWMreh81heBVuoTTK8 # PuXtRQgRMRKwDeTxlc6p+zba4mIEYG8rqJtPFRgViNCJ1KsgSIowup3BNU05YuFn # NoPoRayMDVMgejVgJin3Mg2DCYvt/+MBmO4IoggWlFsXj59uUgA= # =DXnZ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 25 Apr 2025 11:26:55 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'single-binary-20250425' of https://github.com/philmd/qemu: (58 commits) qemu: Convert target_name() to TargetInfo API accel: Move target-agnostic code from accel-target.c -> accel-common.c accel: Make AccelCPUClass structure target-agnostic accel: Include missing 'qemu/accel.h' header in accel-internal.h accel: Implement accel_init_ops_interfaces() for both system/user mode cpus: Move target-agnostic methods out of cpu-target.c cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type() qemu: Introduce target_cpu_type() qapi: Rename TargetInfo structure as QemuTargetInfo hw/microblaze: Evaluate TARGET_BIG_ENDIAN at compile time hw/mips: Evaluate TARGET_BIG_ENDIAN at compile time target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile time target/mips: Check CPU endianness at runtime using env_is_bigendian() accel/kvm: Use target_needs_bswap() linux-user/elfload: Use target_needs_bswap() target/hexagon: Include missing 'accel/tcg/getpc.h' accel/tcg: Correct list of included headers in tcg-stub.c system/kvm: make functions accessible from common code meson: Use osdep_prefix for strchrnul() meson: Share common C source prefixes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
357 lines
9.7 KiB
C
357 lines
9.7 KiB
C
/*
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* iommufd container backend
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*
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* Copyright (C) 2023 Intel Corporation.
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* Copyright Red Hat, Inc. 2023
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*
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* Authors: Yi Liu <yi.l.liu@intel.com>
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* Eric Auger <eric.auger@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "system/iommufd.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "qom/object_interfaces.h"
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#include "qemu/error-report.h"
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#include "monitor/monitor.h"
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#include "trace.h"
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#include "hw/vfio/vfio-device.h"
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#include <sys/ioctl.h>
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#include <linux/iommufd.h>
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static void iommufd_backend_init(Object *obj)
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{
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IOMMUFDBackend *be = IOMMUFD_BACKEND(obj);
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be->fd = -1;
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be->users = 0;
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be->owned = true;
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}
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static void iommufd_backend_finalize(Object *obj)
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{
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IOMMUFDBackend *be = IOMMUFD_BACKEND(obj);
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if (be->owned) {
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close(be->fd);
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be->fd = -1;
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}
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}
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static void iommufd_backend_set_fd(Object *obj, const char *str, Error **errp)
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{
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ERRP_GUARD();
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IOMMUFDBackend *be = IOMMUFD_BACKEND(obj);
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int fd = -1;
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fd = monitor_fd_param(monitor_cur(), str, errp);
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if (fd == -1) {
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error_prepend(errp, "Could not parse remote object fd %s:", str);
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return;
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}
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be->fd = fd;
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be->owned = false;
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trace_iommu_backend_set_fd(be->fd);
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}
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static bool iommufd_backend_can_be_deleted(UserCreatable *uc)
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{
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IOMMUFDBackend *be = IOMMUFD_BACKEND(uc);
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return !be->users;
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}
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static void iommufd_backend_class_init(ObjectClass *oc, const void *data)
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{
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UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
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ucc->can_be_deleted = iommufd_backend_can_be_deleted;
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object_class_property_add_str(oc, "fd", NULL, iommufd_backend_set_fd);
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}
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bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp)
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{
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int fd;
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if (be->owned && !be->users) {
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fd = qemu_open("/dev/iommu", O_RDWR, errp);
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if (fd < 0) {
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return false;
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}
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be->fd = fd;
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}
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be->users++;
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trace_iommufd_backend_connect(be->fd, be->owned, be->users);
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return true;
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}
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void iommufd_backend_disconnect(IOMMUFDBackend *be)
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{
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if (!be->users) {
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goto out;
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}
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be->users--;
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if (!be->users && be->owned) {
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close(be->fd);
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be->fd = -1;
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}
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out:
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trace_iommufd_backend_disconnect(be->fd, be->users);
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}
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bool iommufd_backend_alloc_ioas(IOMMUFDBackend *be, uint32_t *ioas_id,
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Error **errp)
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{
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int fd = be->fd;
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struct iommu_ioas_alloc alloc_data = {
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.size = sizeof(alloc_data),
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.flags = 0,
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};
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if (ioctl(fd, IOMMU_IOAS_ALLOC, &alloc_data)) {
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error_setg_errno(errp, errno, "Failed to allocate ioas");
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return false;
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}
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*ioas_id = alloc_data.out_ioas_id;
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trace_iommufd_backend_alloc_ioas(fd, *ioas_id);
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return true;
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}
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void iommufd_backend_free_id(IOMMUFDBackend *be, uint32_t id)
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{
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int ret, fd = be->fd;
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struct iommu_destroy des = {
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.size = sizeof(des),
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.id = id,
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};
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ret = ioctl(fd, IOMMU_DESTROY, &des);
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trace_iommufd_backend_free_id(fd, id, ret);
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if (ret) {
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error_report("Failed to free id: %u %m", id);
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}
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}
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int iommufd_backend_map_dma(IOMMUFDBackend *be, uint32_t ioas_id, hwaddr iova,
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ram_addr_t size, void *vaddr, bool readonly)
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{
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int ret, fd = be->fd;
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struct iommu_ioas_map map = {
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.size = sizeof(map),
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.flags = IOMMU_IOAS_MAP_READABLE |
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IOMMU_IOAS_MAP_FIXED_IOVA,
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.ioas_id = ioas_id,
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.__reserved = 0,
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.user_va = (uintptr_t)vaddr,
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.iova = iova,
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.length = size,
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};
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if (!readonly) {
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map.flags |= IOMMU_IOAS_MAP_WRITEABLE;
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}
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ret = ioctl(fd, IOMMU_IOAS_MAP, &map);
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trace_iommufd_backend_map_dma(fd, ioas_id, iova, size,
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vaddr, readonly, ret);
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if (ret) {
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ret = -errno;
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/* TODO: Not support mapping hardware PCI BAR region for now. */
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if (errno == EFAULT) {
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warn_report("IOMMU_IOAS_MAP failed: %m, PCI BAR?");
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}
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}
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return ret;
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}
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int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint32_t ioas_id,
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hwaddr iova, ram_addr_t size)
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{
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int ret, fd = be->fd;
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struct iommu_ioas_unmap unmap = {
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.size = sizeof(unmap),
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.ioas_id = ioas_id,
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.iova = iova,
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.length = size,
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};
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ret = ioctl(fd, IOMMU_IOAS_UNMAP, &unmap);
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/*
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* IOMMUFD takes mapping as some kind of object, unmapping
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* nonexistent mapping is treated as deleting a nonexistent
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* object and return ENOENT. This is different from legacy
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* backend which allows it. vIOMMU may trigger a lot of
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* redundant unmapping, to avoid flush the log, treat them
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* as succeess for IOMMUFD just like legacy backend.
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*/
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if (ret && errno == ENOENT) {
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trace_iommufd_backend_unmap_dma_non_exist(fd, ioas_id, iova, size, ret);
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ret = 0;
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} else {
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trace_iommufd_backend_unmap_dma(fd, ioas_id, iova, size, ret);
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}
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if (ret) {
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ret = -errno;
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}
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return ret;
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}
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bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,
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uint32_t pt_id, uint32_t flags,
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uint32_t data_type, uint32_t data_len,
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void *data_ptr, uint32_t *out_hwpt,
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Error **errp)
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{
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int ret, fd = be->fd;
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struct iommu_hwpt_alloc alloc_hwpt = {
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.size = sizeof(struct iommu_hwpt_alloc),
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.flags = flags,
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.dev_id = dev_id,
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.pt_id = pt_id,
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.data_type = data_type,
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.data_len = data_len,
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.data_uptr = (uintptr_t)data_ptr,
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};
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ret = ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt);
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trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type,
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data_len, (uintptr_t)data_ptr,
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alloc_hwpt.out_hwpt_id, ret);
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if (ret) {
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error_setg_errno(errp, errno, "Failed to allocate hwpt");
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return false;
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}
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*out_hwpt = alloc_hwpt.out_hwpt_id;
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return true;
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}
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bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be,
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uint32_t hwpt_id, bool start,
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Error **errp)
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{
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int ret;
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struct iommu_hwpt_set_dirty_tracking set_dirty = {
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.size = sizeof(set_dirty),
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.hwpt_id = hwpt_id,
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.flags = start ? IOMMU_HWPT_DIRTY_TRACKING_ENABLE : 0,
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};
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ret = ioctl(be->fd, IOMMU_HWPT_SET_DIRTY_TRACKING, &set_dirty);
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trace_iommufd_backend_set_dirty(be->fd, hwpt_id, start, ret ? errno : 0);
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if (ret) {
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error_setg_errno(errp, errno,
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"IOMMU_HWPT_SET_DIRTY_TRACKING(hwpt_id %u) failed",
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hwpt_id);
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return false;
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}
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return true;
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}
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bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be,
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uint32_t hwpt_id,
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uint64_t iova, ram_addr_t size,
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uint64_t page_size, uint64_t *data,
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Error **errp)
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{
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int ret;
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struct iommu_hwpt_get_dirty_bitmap get_dirty_bitmap = {
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.size = sizeof(get_dirty_bitmap),
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.hwpt_id = hwpt_id,
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.iova = iova,
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.length = size,
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.page_size = page_size,
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.data = (uintptr_t)data,
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};
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ret = ioctl(be->fd, IOMMU_HWPT_GET_DIRTY_BITMAP, &get_dirty_bitmap);
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trace_iommufd_backend_get_dirty_bitmap(be->fd, hwpt_id, iova, size,
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page_size, ret ? errno : 0);
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if (ret) {
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error_setg_errno(errp, errno,
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"IOMMU_HWPT_GET_DIRTY_BITMAP (iova: 0x%"HWADDR_PRIx
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" size: 0x"RAM_ADDR_FMT") failed", iova, size);
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return false;
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}
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return true;
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}
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bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid,
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uint32_t *type, void *data, uint32_t len,
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uint64_t *caps, Error **errp)
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{
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struct iommu_hw_info info = {
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.size = sizeof(info),
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.dev_id = devid,
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.data_len = len,
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.data_uptr = (uintptr_t)data,
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};
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if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) {
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error_setg_errno(errp, errno, "Failed to get hardware info");
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return false;
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}
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g_assert(type);
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*type = info.out_data_type;
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g_assert(caps);
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*caps = info.out_capabilities;
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return true;
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}
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static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **errp)
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{
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HostIOMMUDeviceCaps *caps = &hiod->caps;
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switch (cap) {
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case HOST_IOMMU_DEVICE_CAP_IOMMU_TYPE:
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return caps->type;
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case HOST_IOMMU_DEVICE_CAP_AW_BITS:
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return vfio_device_get_aw_bits(hiod->agent);
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default:
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error_setg(errp, "%s: unsupported capability %x", hiod->name, cap);
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return -EINVAL;
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}
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}
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static void hiod_iommufd_class_init(ObjectClass *oc, const void *data)
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{
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HostIOMMUDeviceClass *hioc = HOST_IOMMU_DEVICE_CLASS(oc);
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hioc->get_cap = hiod_iommufd_get_cap;
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};
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static const TypeInfo types[] = {
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{
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.name = TYPE_IOMMUFD_BACKEND,
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.parent = TYPE_OBJECT,
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.instance_size = sizeof(IOMMUFDBackend),
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.instance_init = iommufd_backend_init,
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.instance_finalize = iommufd_backend_finalize,
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.class_size = sizeof(IOMMUFDBackendClass),
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.class_init = iommufd_backend_class_init,
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.interfaces = (const InterfaceInfo[]) {
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{ TYPE_USER_CREATABLE },
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{ }
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}
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}, {
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.name = TYPE_HOST_IOMMU_DEVICE_IOMMUFD,
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.parent = TYPE_HOST_IOMMU_DEVICE,
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.class_init = hiod_iommufd_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(types)
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