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7fa0f4a70c
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* TranslationBlock internal declarations (target specific)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H
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#define ACCEL_TCG_TB_INTERNAL_TARGET_H
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#include "exec/translation-block.h"
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/*
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* The true return address will often point to a host insn that is part of
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* the next translated guest insn. Adjust the address backward to point to
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* the middle of the call insn. Subtracting one would do the job except for
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* several compressed mode architectures (arm, mips) which set the low bit
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* to indicate the compressed mode; subtracting two works around that. It
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* is also the case that there are no host isas that contain a call insn
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* smaller than 4 bytes, so we don't worry about special-casing this.
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*/
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#define GETPC_ADJ 2
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void tb_lock_page0(tb_page_addr_t);
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#ifdef CONFIG_USER_ONLY
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/*
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* For user-only, page_protect sets the page read-only.
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* Since most execution is already on read-only pages, and we'd need to
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* account for other TBs on the same page, defer undoing any page protection
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* until we receive the write fault.
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*/
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static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1)
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{
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tb_lock_page0(p1);
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}
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static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { }
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static inline void tb_unlock_pages(TranslationBlock *tb) { }
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#else
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void tb_lock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_pages(TranslationBlock *);
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#endif
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#ifdef CONFIG_SOFTMMU
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void tb_invalidate_phys_range_fast(CPUState *cpu, ram_addr_t ram_addr,
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unsigned size, uintptr_t retaddr);
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#endif /* CONFIG_SOFTMMU */
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bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr,
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uintptr_t pc);
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#endif
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