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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
142 lines
4 KiB
C
142 lines
4 KiB
C
/*
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* Internal execution defines for qemu (target agnostic)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_INTERNAL_COMMON_H
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#define ACCEL_TCG_INTERNAL_COMMON_H
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#include "exec/cpu-common.h"
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#include "exec/translation-block.h"
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#include "exec/mmap-lock.h"
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#include "accel/tcg/tb-cpu-state.h"
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extern int64_t max_delay;
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extern int64_t max_advance;
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extern bool one_insn_per_tb;
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extern bool icount_align_option;
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/*
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* Return true if CS is not running in parallel with other cpus, either
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* because there are no other cpus or we are within an exclusive context.
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*/
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static inline bool cpu_in_serial_context(CPUState *cs)
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{
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return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs);
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}
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/**
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* cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
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* @cs: CPUState pointer
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*
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* The memory callbacks are installed if a plugin has instrumented an
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* instruction for memory. This can be useful to know if you want to
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* force a slow path for a series of memory accesses.
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*/
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static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu)
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{
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#ifdef CONFIG_PLUGIN
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return !!cpu->neg.plugin_mem_cbs;
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#else
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return false;
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#endif
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}
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TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s);
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void page_init(void);
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void tb_htable_init(void);
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void tb_reset_jump(TranslationBlock *tb, int n);
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TranslationBlock *tb_link_page(TranslationBlock *tb);
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void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
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uintptr_t host_pc);
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/**
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* tlb_init - initialize a CPU's TLB
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* @cpu: CPU whose TLB should be initialized
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*/
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void tlb_init(CPUState *cpu);
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/**
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* tlb_destroy - destroy a CPU's TLB
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* @cpu: CPU whose TLB should be destroyed
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*/
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void tlb_destroy(CPUState *cpu);
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bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
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void tcg_exec_unrealizefn(CPUState *cpu);
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/* current cflags for hashing/comparison */
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uint32_t curr_cflags(CPUState *cpu);
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void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
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/**
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* get_page_addr_code_hostp()
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* @env: CPUArchState
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* @addr: guest virtual address of guest code
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*
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* See get_page_addr_code() (full-system version) for documentation on the
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* return value.
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*
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* Sets *@hostp (when @hostp is non-NULL) as follows.
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* If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
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* to the host address where @addr's content is kept.
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*
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* Note: this function can trigger an exception.
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*/
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tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
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void **hostp);
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/**
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* get_page_addr_code()
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* @env: CPUArchState
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* @addr: guest virtual address of guest code
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*
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* If we cannot translate and execute from the entire RAM page, or if
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* the region is not backed by RAM, returns -1. Otherwise, returns the
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* ram_addr_t corresponding to the guest code at @addr.
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*
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* Note: this function can trigger an exception.
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*/
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static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
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vaddr addr)
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{
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return get_page_addr_code_hostp(env, addr, NULL);
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}
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/*
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* Access to the various translations structures need to be serialised
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* via locks for consistency. In user-mode emulation access to the
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* memory related structures are protected with mmap_lock.
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* In !user-mode we use per-page locks.
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*/
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#ifdef CONFIG_USER_ONLY
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#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
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#else
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#define assert_memory_lock()
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#endif
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#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG)
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void assert_no_pages_locked(void);
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#else
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static inline void assert_no_pages_locked(void) { }
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#endif
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#ifdef CONFIG_USER_ONLY
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static inline void page_table_config_init(void) { }
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#else
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void page_table_config_init(void);
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#endif
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#ifndef CONFIG_USER_ONLY
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G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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#endif /* CONFIG_USER_ONLY */
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
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#endif
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