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This patch fixes an obscure failure of the QNX kernel on QEMU x86 SMP. In QNX, all hardware interrupts come via the PIC, and are delivered by the cpu 0 LAPIC in ExtINT mode, while IPIs are delivered by the LAPIC in fixed mode. This bug happens as follows: - cpu 0 masks a particular PIC interrupt - IPI sent to cpu 0 (CPU_INTERRUPT_HARD is set) - before the IPI is accepted, the masked interrupt line is asserted by the device Since the interrupt is masked, apic_deliver_pic_intr will clear CPU_INTERRUPT_HARD. The IPI will still be set in the APIC irr, but since CPU_INTERRUPT_HARD is not set the cpu will not notice. Depending on the scenario this can cause a system hang, i.e. if cpu 0 is expected to unmask the interrupt. In order to fix this, do a full check of the APIC before an EXTINT is acknowledged. This can result in clearing CPU_INTERRUPT_HARD, but can also result in delivering the lost IPI. Reported-by: Richard Bilson <rbilson@qnx.com> Tested-by: Richard Bilson <rbilson@qnx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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| .. | ||
| allwinner-a10-pic.c | ||
| apic.c | ||
| apic_common.c | ||
| arm_gic.c | ||
| arm_gic_common.c | ||
| arm_gic_kvm.c | ||
| armv7m_nvic.c | ||
| etraxfs_pic.c | ||
| exynos4210_combiner.c | ||
| exynos4210_gic.c | ||
| gic_internal.h | ||
| grlib_irqmp.c | ||
| heathrow_pic.c | ||
| i8259.c | ||
| i8259_common.c | ||
| imx_avic.c | ||
| ioapic.c | ||
| ioapic_common.c | ||
| lm32_pic.c | ||
| Makefile.objs | ||
| omap_intc.c | ||
| openpic.c | ||
| openpic_kvm.c | ||
| pl190.c | ||
| puv3_intc.c | ||
| realview_gic.c | ||
| s390_flic.c | ||
| s390_flic_kvm.c | ||
| sh_intc.c | ||
| slavio_intctl.c | ||
| xics.c | ||
| xics_kvm.c | ||
| xilinx_intc.c | ||