LIU Zhiwei 5e54b439f5 target/riscv: Relax fld alignment requirement ... According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-08-06 14:18:41 +10:00
..
trans_privileged.c.inc	trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint	2024-06-03 11:12:12 +10:00
trans_rva.c.inc	target/riscv: Move gen_amo before implement Zabha	2024-07-18 12:00:42 +10:00
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	2024-03-22 15:24:37 +10:00
trans_rvd.c.inc	target/riscv: Relax fld alignment requirement	2024-08-06 14:18:41 +10:00
trans_rvf.c.inc	target/riscv: Remove redundant insn length check for zama16b	2024-08-06 14:15:09 +10:00
trans_rvh.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvi.c.inc	target/riscv: Remove redundant insn length check for zama16b	2024-08-06 14:15:09 +10:00
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvv.c.inc	target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions	2024-06-03 11:12:12 +10:00
trans_rvvk.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	2024-03-22 15:24:37 +10:00
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	2024-07-18 12:00:42 +10:00
trans_rvzacas.c.inc	target/riscv: Move gen_cmpxchg before adding amocas.[b|h]	2024-07-18 12:00:42 +10:00
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
trans_rvzce.c.inc	target/riscv: Update $ra with current $pc in trans_cm_jalt()	2024-03-08 15:37:20 +10:00
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	2024-06-03 11:12:12 +10:00
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2023-05-05 10:49:50 +10:00
trans_rvzimop.c.inc	target/riscv: Add zimop extension	2024-07-18 12:00:42 +10:00
trans_svinval.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2023-05-05 10:49:50 +10:00