Richard Henderson 3ab6e68cd0 accel/tcg: Add tlb_flush_page_bits_by_mmuidx* ... On ARM, the Top Byte Ignore feature means that only 56 bits of the address are significant in the virtual address. We are required to give the entire 64-bit address to FAR_ELx on fault, which means that we do not "clean" the top byte early in TCG. This new interface allows us to flush all 256 possible aliases for a given page, currently missed by tlb_flush_page*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201016210754.818257-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-10-20 16:12:00 +01:00
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kvm	kvm: kvm_init_vcpu take Error pointer	2020-10-05 16:41:22 +02:00
qtest	cpus: extract out qtest-specific code to accel/qtest	2020-10-05 16:41:22 +02:00
stubs	kvm: remove kvm specific functions from global includes	2020-10-05 16:41:22 +02:00
tcg	accel/tcg: Add tlb_flush_page_bits_by_mmuidx*	2020-10-20 16:12:00 +01:00
xen	meson: accel	2020-08-21 06:30:36 -04:00
accel.c	accel: Introduce the current_accel() wrapper	2020-01-24 20:59:11 +01:00
Kconfig	accel/Kconfig: Add the TCG selector	2020-07-10 18:02:21 -04:00
meson.build	cpus: extract out qtest-specific code to accel/qtest	2020-10-05 16:41:22 +02:00