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7cb1e61851
There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
116 lines
5.1 KiB
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116 lines
5.1 KiB
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A-profile CPU architecture support
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==================================
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QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
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Armv8 versions of the A-profile architecture. It also has support for
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the following architecture extensions:
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- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
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- FEAT_AA32HPD (AArch32 hierarchical permission disables)
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- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
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- FEAT_AES (AESD and AESE instructions)
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- FEAT_BBM at level 2 (Translation table break-before-make levels)
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- FEAT_BF16 (AArch64 BFloat16 instructions)
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- FEAT_BTI (Branch Target Identification)
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- FEAT_CSV2 (Cache speculation variant 2)
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- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
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- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
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- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
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- FEAT_DIT (Data Independent Timing instructions)
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- FEAT_DPB (DC CVAP instruction)
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- FEAT_Debugv8p2 (Debug changes for v8.2)
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- FEAT_Debugv8p4 (Debug changes for v8.4)
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- FEAT_DotProd (Advanced SIMD dot product instructions)
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- FEAT_FCMA (Floating-point complex number instructions)
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- FEAT_FHM (Floating-point half-precision multiplication instructions)
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- FEAT_FP16 (Half-precision floating-point data processing)
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- FEAT_FRINTTS (Floating-point to integer instructions)
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- FEAT_FlagM (Flag manipulation instructions v2)
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- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
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- FEAT_HPDS (Hierarchical permission disables)
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- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
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- FEAT_IESB (Implicit error synchronization event)
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- FEAT_JSCVT (JavaScript conversion instructions)
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- FEAT_LOR (Limited ordering regions)
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- FEAT_LPA (Large Physical Address space)
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- FEAT_LPA2 (Large Physical and virtual Address space v2)
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- FEAT_LRCPC (Load-acquire RCpc instructions)
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- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
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- FEAT_LSE (Large System Extensions)
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- FEAT_LVA (Large Virtual Address space)
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- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
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- FEAT_MTE3 (MTE Asymmetric Fault Handling)
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- FEAT_PAN (Privileged access never)
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- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
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- FEAT_PAuth (Pointer authentication)
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- FEAT_PMULL (PMULL, PMULL2 instructions)
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- FEAT_PMUv3p1 (PMU Extensions v3.1)
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- FEAT_PMUv3p4 (PMU Extensions v3.4)
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- FEAT_RAS (Reliability, availability, and serviceability)
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- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
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- FEAT_RNG (Random number generator)
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- FEAT_SB (Speculation Barrier)
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- FEAT_SEL2 (Secure EL2)
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- FEAT_SHA1 (SHA1 instructions)
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- FEAT_SHA256 (SHA256 instructions)
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- FEAT_SHA3 (Advanced SIMD SHA3 instructions)
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- FEAT_SHA512 (Advanced SIMD SHA512 instructions)
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- FEAT_SM3 (Advanced SIMD SM3 instructions)
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- FEAT_SM4 (Advanced SIMD SM4 instructions)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
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- FEAT_TLBIRANGE (TLB invalidate range instructions)
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- FEAT_TTCNP (Translation table Common not private translations)
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- FEAT_TTL (Translation Table Level)
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- FEAT_TTST (Small translation tables)
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- FEAT_UAO (Unprivileged Access Override control)
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- FEAT_VHE (Virtualization Host Extensions)
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- FEAT_VMID16 (16-bit VMID)
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- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
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- SVE (The Scalable Vector Extension)
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- SVE2 (The Scalable Vector Extension v2)
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For information on the specifics of these extensions, please refer
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to the `Armv8-A Arm Architecture Reference Manual
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<https://developer.arm.com/documentation/ddi0487/latest>`_.
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When a specific named CPU is being emulated, only those features which
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are present in hardware for that CPU are emulated. (If a feature is
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not in the list above then it is not supported, even if the real
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hardware should have it.) The ``max`` CPU enables all features.
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R-profile CPU architecture support
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==================================
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QEMU's TCG emulation support for R-profile CPUs is currently limited.
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We emulate only the Cortex-R5 and Cortex-R5F CPUs.
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M-profile CPU architecture support
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==================================
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QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
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Armv8.1-M versions of the M-profile architucture. It also has support
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for the following architecture extensions:
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- FP (Floating-point Extension)
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- FPCXT (FPCXT access instructions)
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- HP (Half-precision floating-point instructions)
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- LOB (Low Overhead loops and Branch future)
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- M (Main Extension)
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- MPU (Memory Protection Unit Extension)
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- PXN (Privileged Execute Never)
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- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only
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- S (Security Extension)
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- ST (System Timer Extension)
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For information on the specifics of these extensions, please refer
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to the `Armv8-M Arm Architecture Reference Manual
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<https://developer.arm.com/documentation/ddi0553/latest>`_.
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When a specific named CPU is being emulated, only those features which
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are present in hardware for that CPU are emulated. (If a feature is
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not in the list above then it is not supported, even if the real
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hardware should have it.) There is no equivalent of the ``max`` CPU for
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M-profile.
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