balrog 7997d92f2c ARM: fix CPS masks (Vincent Palatin). ... According to ARM Reference Manual (DDI0100 A4.1.16), bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask should be 0x0ff10020 not 0x0ff10010. Besides, mmod flag is bit 17 (b14 is SBZ) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162		2008-07-19 10:34:35 +00:00
..
cpu.h	Move interrupt_request and user_mode_only to common cpu state.	2008-07-01 20:01:19 +00:00
exec.h	ARM TCG conversion 13/16.	2008-03-31 03:48:01 +00:00
helper.c	Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).	2008-07-19 10:12:22 +00:00
helpers.h	ARM TCG conversion 15/16.	2008-03-31 03:49:05 +00:00
iwmmxt_helper.c	ARM TCG conversion 15/16.	2008-03-31 03:49:05 +00:00
machine.c	Move CPU save/load registration to common code.	2008-06-30 16:31:04 +00:00
neon_helper.c	Fix few spelling issues in comments	2008-04-11 04:55:07 +00:00
op_addsub.h	ARM TCG conversion 7/16.	2008-03-31 03:46:33 +00:00
op_helper.c	Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).	2008-07-19 10:12:22 +00:00
translate.c	ARM: fix CPS masks (Vincent Palatin).	2008-07-19 10:34:35 +00:00