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a7e8e30e7c
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
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# gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
target/arm: Enable SCTLR_EL1.TIDCP for user-only
target/arm: Implement FEAT_TIDCP1
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement cortex-a710
target/arm: Implement RMR_ELx
arm64: Restore trapless ptimer access
target/arm: Do not use gen_mte_checkN in trans_STGP
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc: Introduce the Xilinx CFI interface
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_Pauth2
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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| .. | ||
| acpi | ||
| adc | ||
| arm | ||
| audio | ||
| block | ||
| char | ||
| core | ||
| cpu | ||
| cris | ||
| cxl | ||
| display | ||
| dma | ||
| firmware | ||
| gpio | ||
| hyperv | ||
| i2c | ||
| i386 | ||
| ide | ||
| input | ||
| intc | ||
| ipack | ||
| ipmi | ||
| isa | ||
| loongarch | ||
| m68k | ||
| mem | ||
| mips | ||
| misc | ||
| net | ||
| nubus | ||
| nvram | ||
| openrisc | ||
| pci | ||
| pci-bridge | ||
| pci-host | ||
| ppc | ||
| rdma | ||
| remote | ||
| riscv | ||
| rtc | ||
| rx | ||
| s390x | ||
| scsi | ||
| sd | ||
| sensor | ||
| sh4 | ||
| southbridge | ||
| sparc | ||
| ssi | ||
| timer | ||
| tricore | ||
| usb | ||
| vfio | ||
| virtio | ||
| watchdog | ||
| xen | ||
| xtensa | ||
| boards.h | ||
| clock.h | ||
| elf_ops.h | ||
| fw-path-provider.h | ||
| hotplug.h | ||
| hw.h | ||
| ide.h | ||
| irq.h | ||
| loader-fit.h | ||
| loader.h | ||
| nmi.h | ||
| or-irq.h | ||
| pcmcia.h | ||
| platform-bus.h | ||
| ptimer.h | ||
| qdev-clock.h | ||
| qdev-core.h | ||
| qdev-dma.h | ||
| qdev-properties-system.h | ||
| qdev-properties.h | ||
| register.h | ||
| registerfields.h | ||
| resettable.h | ||
| stream.h | ||
| sysbus.h | ||
| usb.h | ||
| vmstate-if.h | ||