Richard Henderson 7667cafd5a target/riscv: Replace DisasContext.w with DisasContext.ol ... In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 07:47:51 +10:00
..
trans_privileged.c.inc	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
trans_rva.c.inc	target/riscv: Use {get,dest}_gpr for RVA	2021-09-01 11:59:12 +10:00
trans_rvb.c.inc	target/riscv: Replace DisasContext.w with DisasContext.ol	2021-10-22 07:47:51 +10:00
trans_rvd.c.inc	target/riscv: Use {get,dest}_gpr for RVD	2021-09-01 11:59:12 +10:00
trans_rvf.c.inc	target/riscv: Use {get,dest}_gpr for RVF	2021-09-01 11:59:12 +10:00
trans_rvh.c.inc	target/riscv: Tidy trans_rvh.c.inc	2021-09-01 11:59:12 +10:00
trans_rvi.c.inc	target/riscv: Replace DisasContext.w with DisasContext.ol	2021-10-22 07:47:51 +10:00
trans_rvm.c.inc	target/riscv: Replace DisasContext.w with DisasContext.ol	2021-10-22 07:47:51 +10:00
trans_rvv.c.inc	target/riscv: Properly check SEW in amo_op	2021-10-22 07:47:51 +10:00