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76116e28e1
* Experimantal support for writable misa. * Support for Svadu extension. * Support for the Zicond extension. * Fixes to gdbstub, CSR accesses, dependencies between the various floating-point exceptions, and XTheadMemPair. * Many cleanups. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBrrUTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYicHrD/9dHBDOYNwyT/C2Q31NHMcEsVN6J0kW 0sVyDb2/TUFoXmClMwS6jZYQQwWD7tjjB7BDcvPJ0QKLblDoZFX5JyxpQypIKWcs It/E6mk7aG0epH1GoB/mbHFDbeCm4tbo7Vf6cQGpV/vGWBUaOS67c5nenUK7Tlqw NTr9qak+9NYVswvMHZ0lUKtO12W1g/1EVkict2/90P2snWbPZ+foWomifGNljmhy 5WtCNp27uBKF/uuD9xubLOxSEcqtZFTuKJy7U3azV4I0IKfd6Is83Kd0IwBOrTgT MYkFdtQE1jgbkXYVZjft6ymLuqJrcLFYwD8C2zdNAXJLk1Y+MCtGafgW6f6SkT6B FrNaSOqQ9xXiaNStF2FwYdmZ476zcY+eEg2rH1grTwCMewZ9r7m3+H8iat/tR0pt 9scYAre1oaL33LB6DGZi3JkssNYyj42sutcNao2hQXRHcsh+vv1dLR+Di2mO6Ji5 MNfvEgCrWWZjNVSwvhwCXdJPqqpyTbkRf8HJEp0gWvjk6VoF8sWidDw/8oMLj+wW qZur7GNe+piJNvly85aFSL9J3SX7RyNeDzX/yK3b4k+g6I/ZziQaNgQtB9gYcm6w mj3snCwRbEMEhdhPH0+Chm0Wb97knHJS14Vq9wCe2xh16o3HM5FspboLFkGZMjDV tRDPFb7pitwdlA== =FMkl -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu into staging Fifth RISC-V PR for QEMU 8.0 * Experimantal support for writable misa. * Support for Svadu extension. * Support for the Zicond extension. * Fixes to gdbstub, CSR accesses, dependencies between the various floating-point exceptions, and XTheadMemPair. * Many cleanups. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBrrUTHHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYicHrD/9dHBDOYNwyT/C2Q31NHMcEsVN6J0kW # 0sVyDb2/TUFoXmClMwS6jZYQQwWD7tjjB7BDcvPJ0QKLblDoZFX5JyxpQypIKWcs # It/E6mk7aG0epH1GoB/mbHFDbeCm4tbo7Vf6cQGpV/vGWBUaOS67c5nenUK7Tlqw # NTr9qak+9NYVswvMHZ0lUKtO12W1g/1EVkict2/90P2snWbPZ+foWomifGNljmhy # 5WtCNp27uBKF/uuD9xubLOxSEcqtZFTuKJy7U3azV4I0IKfd6Is83Kd0IwBOrTgT # MYkFdtQE1jgbkXYVZjft6ymLuqJrcLFYwD8C2zdNAXJLk1Y+MCtGafgW6f6SkT6B # FrNaSOqQ9xXiaNStF2FwYdmZ476zcY+eEg2rH1grTwCMewZ9r7m3+H8iat/tR0pt # 9scYAre1oaL33LB6DGZi3JkssNYyj42sutcNao2hQXRHcsh+vv1dLR+Di2mO6Ji5 # MNfvEgCrWWZjNVSwvhwCXdJPqqpyTbkRf8HJEp0gWvjk6VoF8sWidDw/8oMLj+wW # qZur7GNe+piJNvly85aFSL9J3SX7RyNeDzX/yK3b4k+g6I/ZziQaNgQtB9gYcm6w # mj3snCwRbEMEhdhPH0+Chm0Wb97knHJS14Vq9wCe2xh16o3HM5FspboLFkGZMjDV # tRDPFb7pitwdlA== # =FMkl # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 08:24:21 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu: (59 commits) target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig target/riscv/vector_helper.c: create vext_set_tail_elems_1s() target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers target/riscv/csr.c: simplify mctr() target/riscv/csr.c: use env_archcpu() in ctr() target/riscv: Export Svadu property target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add csr support for svadu target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions hw/riscv: Move the dtb load bits outside of create_fdt() hw/riscv: Skip re-generating DT nodes for a given DTB target/riscv: Add support for Zicond extension RISC-V: XTheadMemPair: Remove register restrictions for store-pair target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages target/riscv: Group all predicate() routines together target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Allow debugger to access sstc CSRs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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