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https://github.com/Motorhead1991/qemu.git
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755e984aa4
So far, the test cases are used for testing SMC model with AST2400 BMC. However, AST2400 is end off live and ASPEED is no longer support this SOC. To test SMC model for AST2500, AST2600 and AST1030, move the test cases from main to test_palmetto_bmc function. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241127091543.1243114-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
659 lines
18 KiB
C
659 lines
18 KiB
C
/*
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* QTest testcase for the M25P80 Flash (Using the Aspeed SPI
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* Controller)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bswap.h"
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#include "libqtest-single.h"
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#include "qemu/bitops.h"
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/*
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* ASPEED SPI Controller registers
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*/
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#define R_CONF 0x00
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#define CONF_ENABLE_W0 (1 << 16)
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#define R_CE_CTRL 0x04
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#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
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#define R_CTRL0 0x10
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#define CTRL_CE_STOP_ACTIVE (1 << 2)
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#define CTRL_READMODE 0x0
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#define CTRL_FREADMODE 0x1
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#define CTRL_WRITEMODE 0x2
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#define CTRL_USERMODE 0x3
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#define SR_WEL BIT(1)
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#define ASPEED_FMC_BASE 0x1E620000
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#define ASPEED_FLASH_BASE 0x20000000
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/*
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* Flash commands
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*/
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enum {
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JEDEC_READ = 0x9f,
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RDSR = 0x5,
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WRDI = 0x4,
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BULK_ERASE = 0xc7,
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READ = 0x03,
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PP = 0x02,
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WRSR = 0x1,
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WREN = 0x6,
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SRWD = 0x80,
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RESET_ENABLE = 0x66,
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RESET_MEMORY = 0x99,
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EN_4BYTE_ADDR = 0xB7,
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ERASE_SECTOR = 0xd8,
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};
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#define FLASH_JEDEC 0x20ba19 /* n25q256a */
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#define FLASH_SIZE (32 * 1024 * 1024)
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#define FLASH_PAGE_SIZE 256
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/*
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* Use an explicit bswap for the values read/wrote to the flash region
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* as they are BE and the Aspeed CPU is LE.
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*/
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static inline uint32_t make_be32(uint32_t data)
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{
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return bswap32(data);
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}
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static void spi_conf(uint32_t value)
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{
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uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
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conf |= value;
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writel(ASPEED_FMC_BASE + R_CONF, conf);
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}
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static void spi_conf_remove(uint32_t value)
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{
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uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
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conf &= ~value;
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writel(ASPEED_FMC_BASE + R_CONF, conf);
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}
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static void spi_ce_ctrl(uint32_t value)
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{
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uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);
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conf |= value;
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writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
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}
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static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
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{
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uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
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ctrl &= ~(CTRL_USERMODE | 0xff << 16);
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ctrl |= mode | (cmd << 16);
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writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
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}
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static void spi_ctrl_start_user(void)
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{
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uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
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ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
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writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
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ctrl &= ~CTRL_CE_STOP_ACTIVE;
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writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
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}
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static void spi_ctrl_stop_user(void)
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{
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uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
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ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
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writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
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}
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static void flash_reset(void)
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{
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
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writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, BULK_ERASE);
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writeb(ASPEED_FLASH_BASE, WRDI);
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spi_ctrl_stop_user();
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spi_conf_remove(CONF_ENABLE_W0);
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}
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static void test_read_jedec(void)
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{
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uint32_t jedec = 0x0;
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, JEDEC_READ);
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jedec |= readb(ASPEED_FLASH_BASE) << 16;
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jedec |= readb(ASPEED_FLASH_BASE) << 8;
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jedec |= readb(ASPEED_FLASH_BASE);
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spi_ctrl_stop_user();
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flash_reset();
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g_assert_cmphex(jedec, ==, FLASH_JEDEC);
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}
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static void read_page(uint32_t addr, uint32_t *page)
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{
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int i;
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, READ);
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writel(ASPEED_FLASH_BASE, make_be32(addr));
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/* Continuous read are supported */
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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page[i] = make_be32(readl(ASPEED_FLASH_BASE));
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}
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spi_ctrl_stop_user();
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}
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static void read_page_mem(uint32_t addr, uint32_t *page)
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{
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int i;
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/* move out USER mode to use direct reads from the AHB bus */
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spi_ctrl_setmode(CTRL_READMODE, READ);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
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}
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}
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static void write_page_mem(uint32_t addr, uint32_t write_value)
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{
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spi_ctrl_setmode(CTRL_WRITEMODE, PP);
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for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
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}
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}
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static void assert_page_mem(uint32_t addr, uint32_t expected_value)
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{
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uint32_t page[FLASH_PAGE_SIZE / 4];
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read_page_mem(addr, page);
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for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, expected_value);
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}
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}
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static void test_erase_sector(void)
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{
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uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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spi_conf(CONF_ENABLE_W0);
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/*
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* Previous page should be full of 0xffs after backend is
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* initialized
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*/
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read_page(some_page_addr - FLASH_PAGE_SIZE, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, PP);
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writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
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/* Fill the page with its own addresses */
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
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}
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spi_ctrl_stop_user();
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/* Check the page is correctly written */
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read_page(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
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}
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
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writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
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spi_ctrl_stop_user();
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/* Check the page is erased */
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read_page(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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flash_reset();
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}
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static void test_erase_all(void)
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{
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uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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spi_conf(CONF_ENABLE_W0);
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/*
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* Previous page should be full of 0xffs after backend is
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* initialized
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*/
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read_page(some_page_addr - FLASH_PAGE_SIZE, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, PP);
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writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
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/* Fill the page with its own addresses */
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
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}
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spi_ctrl_stop_user();
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/* Check the page is correctly written */
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read_page(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
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}
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, BULK_ERASE);
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spi_ctrl_stop_user();
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/* Check the page is erased */
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read_page(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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flash_reset();
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}
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static void test_write_page(void)
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{
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uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
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uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, PP);
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writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
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/* Fill the page with its own addresses */
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
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}
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spi_ctrl_stop_user();
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/* Check what was written */
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read_page(my_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
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}
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/* Check some other page. It should be full of 0xff */
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read_page(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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flash_reset();
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}
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static void test_read_page_mem(void)
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{
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uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
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uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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/*
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* Enable 4BYTE mode for controller. This is should be strapped by
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* HW for CE0 anyhow.
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*/
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spi_ce_ctrl(1 << CRTL_EXTENDED0);
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/* Enable 4BYTE mode for flash. */
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, PP);
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writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
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/* Fill the page with its own addresses */
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
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}
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spi_ctrl_stop_user();
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spi_conf_remove(CONF_ENABLE_W0);
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/* Check what was written */
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read_page_mem(my_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
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}
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/* Check some other page. It should be full of 0xff */
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read_page_mem(some_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, 0xffffffff);
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}
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flash_reset();
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}
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static void test_write_page_mem(void)
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{
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uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE;
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uint32_t page[FLASH_PAGE_SIZE / 4];
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int i;
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/*
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* Enable 4BYTE mode for controller. This is should be strapped by
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* HW for CE0 anyhow.
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*/
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spi_ce_ctrl(1 << CRTL_EXTENDED0);
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/* Enable 4BYTE mode for flash. */
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
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writeb(ASPEED_FLASH_BASE, WREN);
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spi_ctrl_stop_user();
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/* move out USER mode to use direct writes to the AHB bus */
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spi_ctrl_setmode(CTRL_WRITEMODE, PP);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
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make_be32(my_page_addr + i * 4));
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}
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/* Check what was written */
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read_page_mem(my_page_addr, page);
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for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
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g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
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}
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flash_reset();
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}
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static void test_read_status_reg(void)
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{
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uint8_t r;
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spi_conf(CONF_ENABLE_W0);
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, RDSR);
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r = readb(ASPEED_FLASH_BASE);
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spi_ctrl_stop_user();
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g_assert_cmphex(r & SR_WEL, ==, 0);
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g_assert(!qtest_qom_get_bool
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(global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, WREN);
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writeb(ASPEED_FLASH_BASE, RDSR);
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r = readb(ASPEED_FLASH_BASE);
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spi_ctrl_stop_user();
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g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
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g_assert(qtest_qom_get_bool
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(global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
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spi_ctrl_start_user();
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writeb(ASPEED_FLASH_BASE, WRDI);
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writeb(ASPEED_FLASH_BASE, RDSR);
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r = readb(ASPEED_FLASH_BASE);
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spi_ctrl_stop_user();
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g_assert_cmphex(r & SR_WEL, ==, 0);
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g_assert(!qtest_qom_get_bool
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(global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
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flash_reset();
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}
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static void test_status_reg_write_protection(void)
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{
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uint8_t r;
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spi_conf(CONF_ENABLE_W0);
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/* default case: WP# is high and SRWD is low -> status register writable */
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spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
/* test ability to write SRWD */
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, SRWD);
|
|
writeb(ASPEED_FLASH_BASE, RDSR);
|
|
r = readb(ASPEED_FLASH_BASE);
|
|
spi_ctrl_stop_user();
|
|
g_assert_cmphex(r & SRWD, ==, SRWD);
|
|
|
|
/* WP# high and SRWD high -> status register writable */
|
|
spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
/* test ability to write SRWD */
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, 0);
|
|
writeb(ASPEED_FLASH_BASE, RDSR);
|
|
r = readb(ASPEED_FLASH_BASE);
|
|
spi_ctrl_stop_user();
|
|
g_assert_cmphex(r & SRWD, ==, 0);
|
|
|
|
/* WP# low and SRWD low -> status register writable */
|
|
qtest_set_irq_in(global_qtest,
|
|
"/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
|
|
spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
/* test ability to write SRWD */
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, SRWD);
|
|
writeb(ASPEED_FLASH_BASE, RDSR);
|
|
r = readb(ASPEED_FLASH_BASE);
|
|
spi_ctrl_stop_user();
|
|
g_assert_cmphex(r & SRWD, ==, SRWD);
|
|
|
|
/* WP# low and SRWD high -> status register NOT writable */
|
|
spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
/* test ability to write SRWD */
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, 0);
|
|
writeb(ASPEED_FLASH_BASE, RDSR);
|
|
r = readb(ASPEED_FLASH_BASE);
|
|
spi_ctrl_stop_user();
|
|
/* write is not successful */
|
|
g_assert_cmphex(r & SRWD, ==, SRWD);
|
|
|
|
qtest_set_irq_in(global_qtest,
|
|
"/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
|
|
flash_reset();
|
|
}
|
|
|
|
static void test_write_block_protect(void)
|
|
{
|
|
uint32_t sector_size = 65536;
|
|
uint32_t n_sectors = 512;
|
|
|
|
spi_ce_ctrl(1 << CRTL_EXTENDED0);
|
|
spi_conf(CONF_ENABLE_W0);
|
|
|
|
uint32_t bp_bits = 0b0;
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
|
|
|
|
spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
writeb(ASPEED_FLASH_BASE, BULK_ERASE);
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, bp_bits);
|
|
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
spi_ctrl_stop_user();
|
|
|
|
uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
|
|
uint32_t protection_start = n_sectors - num_protected_sectors;
|
|
uint32_t protection_end = n_sectors;
|
|
|
|
for (int sector = 0; sector < n_sectors; sector++) {
|
|
uint32_t addr = sector * sector_size;
|
|
|
|
assert_page_mem(addr, 0xffffffff);
|
|
write_page_mem(addr, make_be32(0xabcdef12));
|
|
|
|
uint32_t expected_value = protection_start <= sector
|
|
&& sector < protection_end
|
|
? 0xffffffff : 0xabcdef12;
|
|
|
|
assert_page_mem(addr, expected_value);
|
|
}
|
|
}
|
|
|
|
flash_reset();
|
|
}
|
|
|
|
static void test_write_block_protect_bottom_bit(void)
|
|
{
|
|
uint32_t sector_size = 65536;
|
|
uint32_t n_sectors = 512;
|
|
|
|
spi_ce_ctrl(1 << CRTL_EXTENDED0);
|
|
spi_conf(CONF_ENABLE_W0);
|
|
|
|
/* top bottom bit is enabled */
|
|
uint32_t bp_bits = 0b00100 << 3;
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
|
|
|
|
spi_ctrl_start_user();
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
writeb(ASPEED_FLASH_BASE, BULK_ERASE);
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
writeb(ASPEED_FLASH_BASE, WRSR);
|
|
writeb(ASPEED_FLASH_BASE, bp_bits);
|
|
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
|
|
writeb(ASPEED_FLASH_BASE, WREN);
|
|
spi_ctrl_stop_user();
|
|
|
|
uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
|
|
uint32_t protection_start = 0;
|
|
uint32_t protection_end = num_protected_sectors;
|
|
|
|
for (int sector = 0; sector < n_sectors; sector++) {
|
|
uint32_t addr = sector * sector_size;
|
|
|
|
assert_page_mem(addr, 0xffffffff);
|
|
write_page_mem(addr, make_be32(0xabcdef12));
|
|
|
|
uint32_t expected_value = protection_start <= sector
|
|
&& sector < protection_end
|
|
? 0xffffffff : 0xabcdef12;
|
|
|
|
assert_page_mem(addr, expected_value);
|
|
}
|
|
}
|
|
|
|
flash_reset();
|
|
}
|
|
|
|
static int test_palmetto_bmc(void)
|
|
{
|
|
g_autofree char *tmp_path = NULL;
|
|
int ret;
|
|
int fd;
|
|
|
|
fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
|
|
g_assert(fd >= 0);
|
|
ret = ftruncate(fd, FLASH_SIZE);
|
|
g_assert(ret == 0);
|
|
close(fd);
|
|
|
|
global_qtest = qtest_initf("-m 256 -machine palmetto-bmc "
|
|
"-drive file=%s,format=raw,if=mtd",
|
|
tmp_path);
|
|
|
|
qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec);
|
|
qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector);
|
|
qtest_add_func("/ast2400/smc/erase_all", test_erase_all);
|
|
qtest_add_func("/ast2400/smc/write_page", test_write_page);
|
|
qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
|
|
qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
|
|
qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
|
|
qtest_add_func("/ast2400/smc/status_reg_write_protection",
|
|
test_status_reg_write_protection);
|
|
qtest_add_func("/ast2400/smc/write_block_protect",
|
|
test_write_block_protect);
|
|
qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
|
|
test_write_block_protect_bottom_bit);
|
|
|
|
flash_reset();
|
|
ret = g_test_run();
|
|
qtest_quit(global_qtest);
|
|
unlink(tmp_path);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
int ret;
|
|
|
|
g_test_init(&argc, &argv, NULL);
|
|
ret = test_palmetto_bmc();
|
|
|
|
return ret;
|
|
}
|