Peter Maydell bc6b1cec84 Make address_space_translate{, _cached}() take a MemTxAttrs argument ... As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate() and address_space_translate_cached(). Callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-4-peter.maydell@linaro.org		2018-05-31 14:50:52 +01:00
..
cpu.c	target/riscv: Honor CPU_DUMP_FPU	2018-05-18 14:52:38 -07:00
cpu.h	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	2018-05-06 10:39:38 +12:00
cpu_bits.h	RISC-V CPU Core Definition	2018-03-07 08:30:28 +13:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	Make address_space_translate{, _cached}() take a MemTxAttrs argument	2018-05-31 14:50:52 +01:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: No traps on writes to misa,minstret,mcycle	2018-05-06 10:39:38 +12:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target-arm queue:	2018-05-11 17:41:54 +01:00