Daniel Henrique Barboza 73afe5c2f9 target/riscv: add shvstvecd ... shvstvecd is defined in RVA22 as: "vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address." This is always true for TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-01-19 09:44:34 +10:00
..
aarch64/virt	tests/acpi: update aarch64/virt/SSDT.memhp	2024-09-17 10:26:27 +02:00
riscv64/virt	target/riscv: add shvstvecd	2025-01-19 09:44:34 +10:00
x86	tests: acpi: update expected blobs	2025-01-15 13:07:25 -05:00
disassemle-aml.sh	acpi/disassemle-aml.sh: fix up after dir reorg	2024-11-04 16:03:24 -05:00
rebuild-expected-aml.sh	tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V	2024-07-03 18:14:07 -04:00