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While we skip the GIC_INTERNAL irqs, we don't change the register offset
accordingly. This will overlap the GICR registers value and leave the
last GIC_INTERNAL irq's registers out of update.
Fix this by skipping the registers banked by GICR.
Also for migration compatibility if the migration source (old version
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
we shift the data of PPI to get the right data for SPI.
Fixes:
|
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|---|---|---|
| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic.h | ||
| arm_gic_common.h | ||
| arm_gicv3.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| armv7m_nvic.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| heathrow_pic.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| mips_gic.h | ||
| realview_gic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||