Jonathan Cameron 638b752da3 pci-bridge/cxl_upstream: Add a CXL switch upstream port ... An initial simple upstream port emulation to allow the creation of CXL switches. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-2-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-06-16 12:54:57 -04:00
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cxl.h	pci-bridge/cxl_upstream: Add a CXL switch upstream port	2022-06-16 12:54:57 -04:00
cxl_component.h	CXL/cxl_component: Add cxl_get_hb_cstate()	2022-05-13 07:57:26 -04:00
cxl_device.h	mem/cxl_type3: Add read and write functions for associated hostmem.	2022-05-13 07:57:26 -04:00
cxl_host.h	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl_pci.h	hw/cxl/device: Add a memory device (8.2.8.5)	2022-05-13 06:13:36 -04:00