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38ba38d87d
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.
To GICINT196 |
ETH1 |-----------| |--------------------------|
-------->|0 | | INTCIO |
ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|
-------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|
ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|
-------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|
UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|
-------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|
UART1 | 22| |--------------------------|
-------->|8 23|
UART2 | 24|
-------->|9 25|
UART3 | 26|
---------|10 27|
UART5 | 28|
-------->|11 29|
UART6 | |
-------->|12 30|
UART7 | 31|
-------->|13 |
UART8 | OR[0:31] |
-------->|14 |
UART9 | |
-------->|15 |
UART10 | |
-------->|16 |
UART11 | |
-------->|17 |
UART12 | |
-------->|18 |
|-----------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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* ASPEED INTC Controller
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*
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* Copyright (C) 2024 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_INTC_H
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#define ASPEED_INTC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "hw/or-irq.h"
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#define TYPE_ASPEED_INTC "aspeed.intc"
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#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
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#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
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OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
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#define ASPEED_INTC_MAX_INPINS 10
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#define ASPEED_INTC_MAX_OUTPINS 19
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typedef struct AspeedINTCIRQ {
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int inpin_idx;
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int outpin_idx;
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int num_outpins;
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uint32_t enable_reg;
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uint32_t status_reg;
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} AspeedINTCIRQ;
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struct AspeedINTCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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MemoryRegion iomem_container;
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uint32_t *regs;
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OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
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qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
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uint32_t enable[ASPEED_INTC_MAX_INPINS];
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uint32_t mask[ASPEED_INTC_MAX_INPINS];
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uint32_t pending[ASPEED_INTC_MAX_INPINS];
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};
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struct AspeedINTCClass {
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SysBusDeviceClass parent_class;
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uint32_t num_lines;
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uint32_t num_inpins;
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uint32_t num_outpins;
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uint64_t mem_size;
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uint64_t nr_regs;
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uint64_t reg_offset;
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const MemoryRegionOps *reg_ops;
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const AspeedINTCIRQ *irq_table;
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int irq_table_count;
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};
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#endif /* ASPEED_INTC_H */
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