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6b4bbd6aeb
In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
145 lines
3.8 KiB
C
145 lines
3.8 KiB
C
/*
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* QEMU OpenRISC timer support
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */
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/* Tick Timer global state to allow all cores to be in sync */
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typedef struct OR1KTimerState {
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uint32_t ttcr;
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uint64_t last_clk;
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} OR1KTimerState;
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static OR1KTimerState *or1k_timer;
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void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val)
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{
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or1k_timer->ttcr = val;
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}
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uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
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{
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return or1k_timer->ttcr;
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}
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/* Add elapsed ticks to ttcr */
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void cpu_openrisc_count_update(OpenRISCCPU *cpu)
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{
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uint64_t now;
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if (!cpu->env.is_counting) {
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return;
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}
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk)
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/ TIMER_PERIOD);
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or1k_timer->last_clk = now;
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}
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/* Update the next timeout time as difference between ttmr and ttcr */
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void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
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{
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uint32_t wait;
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uint64_t now, next;
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if (!cpu->env.is_counting) {
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return;
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}
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cpu_openrisc_count_update(cpu);
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now = or1k_timer->last_clk;
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if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) {
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wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1;
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wait += cpu->env.ttmr & TTMR_TP;
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} else {
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wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP);
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}
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next = now + (uint64_t)wait * TIMER_PERIOD;
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timer_mod(cpu->env.timer, next);
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qemu_cpu_kick(CPU(cpu));
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}
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void cpu_openrisc_count_start(OpenRISCCPU *cpu)
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{
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cpu->env.is_counting = 1;
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cpu_openrisc_count_update(cpu);
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}
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void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
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{
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timer_del(cpu->env.timer);
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cpu_openrisc_count_update(cpu);
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cpu->env.is_counting = 0;
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}
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static void openrisc_timer_cb(void *opaque)
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{
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OpenRISCCPU *cpu = opaque;
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if ((cpu->env.ttmr & TTMR_IE) &&
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timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) {
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CPUState *cs = CPU(cpu);
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cpu->env.ttmr |= TTMR_IP;
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cs->interrupt_request |= CPU_INTERRUPT_TIMER;
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}
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switch (cpu->env.ttmr & TTMR_M) {
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case TIMER_NONE:
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break;
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case TIMER_INTR:
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or1k_timer->ttcr = 0;
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break;
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case TIMER_SHOT:
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cpu_openrisc_count_stop(cpu);
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break;
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case TIMER_CONT:
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break;
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}
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cpu_openrisc_timer_update(cpu);
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}
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static const VMStateDescription vmstate_or1k_timer = {
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.name = "or1k_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ttcr, OR1KTimerState),
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VMSTATE_UINT64(last_clk, OR1KTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
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{
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cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
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cpu->env.ttmr = 0x00000000;
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if (or1k_timer == NULL) {
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or1k_timer = g_new0(OR1KTimerState, 1);
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vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
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}
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}
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