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Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg" class member whose data type is uint_64 to set the different Capability Registers to all ASPEED SOCs. The value of Capability Register is "0x0000000001e80080" for AST2400 and AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
43 lines
1 KiB
C
43 lines
1 KiB
C
/*
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* Aspeed SD Host Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_SDHCI_H
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#define ASPEED_SDHCI_H
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#include "hw/sd/sdhci.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
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#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
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#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
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#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
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OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
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#define ASPEED_SDHCI_NUM_SLOTS 2
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#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
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#define ASPEED_SDHCI_REG_SIZE 0x100
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struct AspeedSDHCIState {
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SysBusDevice parent;
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SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
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uint8_t num_slots;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t regs[ASPEED_SDHCI_NUM_REGS];
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};
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struct AspeedSDHCIClass {
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SysBusDeviceClass parent_class;
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uint64_t capareg;
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};
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#endif /* ASPEED_SDHCI_H */
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