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80e865668d
Stop taking TARGET_VIRT_ADDR_SPACE_BITS into account. Since we currently bound CPU_TLB_DYN_MAX_BITS to 22, the new bound with a 4k page size is 20, which isn't so different. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 lines
296 B
C
13 lines
296 B
C
/*
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* softmmu size bounds
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_TLB_BOUNDS_H
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#define ACCEL_TCG_TLB_BOUNDS_H
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#define CPU_TLB_DYN_MIN_BITS 6
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#define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
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#define CPU_TLB_DYN_DEFAULT_BITS 8
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#endif /* ACCEL_TCG_TLB_BOUNDS_H */
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