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9d88935cb1
PL011 can be in either of 2 modes depending guest config: FIFO and single register. The last mode could be viewed as a 1-element-deep FIFO. Current code open-codes a bunch of depth-dependent logic. Refactor FIFO depth handling code to isolate calculating current FIFO depth. One functional (albeit guest-invisible) side-effect of this change is that previously we would always increment s->read_pos in UARTDR read handler even if FIFO was disabled, now we are limiting read_pos to not exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO). Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| avr_usart.h | ||
| bcm2835_aux.h | ||
| cadence_uart.h | ||
| cmsdk-apb-uart.h | ||
| digic-uart.h | ||
| escc.h | ||
| goldfish_tty.h | ||
| ibex_uart.h | ||
| imx_serial.h | ||
| mchp_pfsoc_mmuart.h | ||
| nrf51_uart.h | ||
| parallel.h | ||
| pl011.h | ||
| renesas_sci.h | ||
| riscv_htif.h | ||
| serial.h | ||
| shakti_uart.h | ||
| sifive_uart.h | ||
| stm32f2xx_usart.h | ||
| xilinx_uartlite.h | ||