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https://github.com/Motorhead1991/qemu.git
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77aad42ee2
Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial configuration is going beyond what it is configured by default because validation should be done on other configurations too. That's why wire also additional uart16500, axi ethernet(with axi dma). GPIOs, i2c and qspi is also listed for completeness. IRQ map is: (addr) 0 - timer (0x41c00000) 1 - uartlite (0x40600000) 2 - i2c (0x40800000) 3 - qspi (0x44a00000) 4 - uart16550 (0x44a10000) 5 - emaclite (0x40e00000) 6 - timer2 (0x41c10000) 7 - axi emac (0x40c00000) 8 - axi dma (0x41e00000) 9 - axi dma 10 - gpio (0x40000000) 11 - gpio2 (0x40010000) 12 - gpio3 (0x40020000) Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
121 lines
2.2 KiB
Text
121 lines
2.2 KiB
Text
config RISCV_IOMMU
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bool
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config RISCV_NUMA
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bool
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config IBEX
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bool
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# RISC-V machines in alphabetical order
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config MICROCHIP_PFSOC
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bool
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default y
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depends on RISCV64
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select CADENCE_SDHCI
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select CPU_CLUSTER
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select DEVICE_TREE
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select MCHP_PFSOC_DMC
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select MCHP_PFSOC_IOSCB
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select MCHP_PFSOC_MMUART
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select MCHP_PFSOC_SYSREG
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select RISCV_ACLINT
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select UNIMP
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config MICROBLAZE_V
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bool
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default y
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depends on RISCV32 || RISCV64
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select XILINX
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select XILINX_AXI
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select XILINX_ETHLITE
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config OPENTITAN
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bool
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default y
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depends on RISCV32
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select IBEX
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select SIFIVE_PLIC
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select UNIMP
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config RISCV_VIRT
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bool
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default y
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depends on RISCV32 || RISCV64
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imply PCI_DEVICES
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imply VIRTIO_VGA
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imply TEST_DEVICES
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imply TPM_TIS_SYSBUS
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select DEVICE_TREE
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select RISCV_NUMA
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select GOLDFISH_RTC
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SERIAL_MM
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select RISCV_ACLINT
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select RISCV_APLIC
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select RISCV_IOMMU
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select RISCV_IMSIC
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select SIFIVE_PLIC
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select SIFIVE_TEST
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select SMBIOS
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select VIRTIO_MMIO
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select FW_CFG_DMA
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select PLATFORM_BUS
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select ACPI
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select ACPI_PCI
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config SHAKTI_C
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bool
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default y
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depends on RISCV64
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select RISCV_ACLINT
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select SHAKTI_UART
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select SIFIVE_PLIC
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select UNIMP
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config SIFIVE_E
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bool
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default y
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depends on RISCV32 || RISCV64
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PLIC
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select SIFIVE_UART
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select SIFIVE_E_PRCI
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select SIFIVE_E_AON
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select UNIMP
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config SIFIVE_U
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bool
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default y
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depends on RISCV32 || RISCV64
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select CADENCE
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select CPU_CLUSTER
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select DEVICE_TREE
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select SIFIVE_SPI
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select SIFIVE_UART
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select SIFIVE_U_OTP
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select SIFIVE_U_PRCI
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select SIFIVE_PWM
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select SSI_M25P80
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select SSI_SD
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select UNIMP
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config SPIKE
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bool
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default y
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depends on RISCV32 || RISCV64
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select DEVICE_TREE
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select RISCV_NUMA
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select HTIF
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select RISCV_ACLINT
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select SIFIVE_PLIC
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