qemu/target/riscv
Daniel Henrique Barboza 608bdebb60 target/riscv/kvm: support KVM_GET_REG_LIST
KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
consists of a KVM ioctl() that retrieves a list of all available regs
for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
supported in the host.

This simplifies our lives when initing the KVM regs since we don't have
to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
always considered fatal, instead of having to handle special error codes
that might indicate a non-fatal failure.

Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
KVM_GET_REG_LIST, so check if we have it available and, in case we
don't, use the legacy() logic.

Otherwise, retrieve the available reg list and use it to check if the
host supports our known KVM regs, doing the usual get_one_reg() for
the supported regs and setting cpu->cfg accordingly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12 12:38:39 +10:00
..
insn_trans tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
kvm target/riscv/kvm: support KVM_GET_REG_LIST 2023-10-12 12:38:39 +10:00
tcg target/riscv/tcg-cpu.c: add extension properties for all cpus 2023-10-12 12:31:17 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add 'max' CPU type 2023-10-12 11:39:33 +10:00
cpu.c target/riscv: add riscv_cpu_get_name() 2023-10-12 12:30:16 +10:00
cpu.h target/riscv: add riscv_cpu_get_name() 2023-10-12 12:30:16 +10:00
cpu_bits.h target/riscv: Update CSR bits name for svadu extension 2023-09-11 11:45:55 +10:00
cpu_cfg.h target/riscv: Add Zihintntl extension ISA string to DTS 2023-09-11 11:45:55 +10:00
cpu_helper.c target/riscv: Update CSR bits name for svadu extension 2023-09-11 11:45:55 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c 2023-10-12 11:57:46 +10:00
debug.c target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
debug.h target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
fpu_helper.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: Restrict KVM-specific fields from ArchCPU 2023-06-28 14:27:59 +02:00
meson.build target/riscv: move KVM only files to kvm subdir 2023-10-12 12:20:24 +10:00
monitor.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
op_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
pmp.c target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes 2023-09-11 11:45:55 +10:00
pmp.h target/riscv: Change the return type of pmp_hart_has_privs() to bool 2023-06-13 17:09:13 +10:00
pmu.c target/riscv/pmu: Restrict 'qemu/log.h' include to source 2023-08-31 19:47:43 +02:00
pmu.h target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c accel/tcg: Replace CPUState.env_ptr with cpu_env() 2023-10-04 11:03:54 -07:00
vcrypto_helper.c target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
vector_helper.c tcg: Correct invalid mentions of 'softmmu' by 'system-mode' 2023-10-07 19:02:33 +02:00
vector_internals.c target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:54 +10:00
vector_internals.h target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:55 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00