mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
5df3fe062f
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
1053 lines
34 KiB
Rust
1053 lines
34 KiB
Rust
// Copyright (C) 2024 Intel Corporation.
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// Author(s): Zhao Liu <zhai1.liu@intel.com>
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// SPDX-License-Identifier: GPL-2.0-or-later
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use std::{
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ffi::{c_int, c_void, CStr},
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pin::Pin,
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ptr::{addr_of_mut, null_mut, NonNull},
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slice::from_ref,
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};
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use qemu_api::{
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bindings::{
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address_space_memory, address_space_stl_le, qdev_prop_bit, qdev_prop_bool,
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qdev_prop_uint32, qdev_prop_uint8,
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},
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c_str,
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cell::{BqlCell, BqlRefCell},
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irq::InterruptSource,
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memory::{
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hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder, MEMTXATTRS_UNSPECIFIED,
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},
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prelude::*,
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qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, ResettablePhasesImpl},
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qom::{ObjectImpl, ObjectType, ParentField},
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qom_isa,
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sysbus::{SysBusDevice, SysBusDeviceImpl},
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timer::{Timer, CLOCK_VIRTUAL, NANOSECONDS_PER_SECOND},
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vmstate::VMStateDescription,
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vmstate_fields, vmstate_of, vmstate_struct, vmstate_subsections, vmstate_validate,
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zeroable::Zeroable,
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};
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use crate::fw_cfg::HPETFwConfig;
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/// Register space for each timer block (`HPET_BASE` is defined in hpet.h).
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const HPET_REG_SPACE_LEN: u64 = 0x400; // 1024 bytes
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/// Minimum recommended hardware implementation.
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const HPET_MIN_TIMERS: u8 = 3;
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/// Maximum timers in each timer block.
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const HPET_MAX_TIMERS: u8 = 32;
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/// Flags that HPETState.flags supports.
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const HPET_FLAG_MSI_SUPPORT_SHIFT: usize = 0;
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const HPET_NUM_IRQ_ROUTES: usize = 32;
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const HPET_LEGACY_PIT_INT: u32 = 0; // HPET_LEGACY_RTC_INT isn't defined here.
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const RTC_ISA_IRQ: usize = 8;
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const HPET_CLK_PERIOD: u64 = 10; // 10 ns
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const FS_PER_NS: u64 = 1000000; // 1000000 femtoseconds == 1 ns
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/// Revision ID (bits 0:7). Revision 1 is implemented (refer to v1.0a spec).
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const HPET_CAP_REV_ID_VALUE: u64 = 0x1;
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const HPET_CAP_REV_ID_SHIFT: usize = 0;
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/// Number of Timers (bits 8:12)
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const HPET_CAP_NUM_TIM_SHIFT: usize = 8;
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/// Counter Size (bit 13)
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const HPET_CAP_COUNT_SIZE_CAP_SHIFT: usize = 13;
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/// Legacy Replacement Route Capable (bit 15)
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const HPET_CAP_LEG_RT_CAP_SHIFT: usize = 15;
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/// Vendor ID (bits 16:31)
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const HPET_CAP_VENDER_ID_VALUE: u64 = 0x8086;
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const HPET_CAP_VENDER_ID_SHIFT: usize = 16;
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/// Main Counter Tick Period (bits 32:63)
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const HPET_CAP_CNT_CLK_PERIOD_SHIFT: usize = 32;
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/// Overall Enable (bit 0)
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const HPET_CFG_ENABLE_SHIFT: usize = 0;
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/// Legacy Replacement Route (bit 1)
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const HPET_CFG_LEG_RT_SHIFT: usize = 1;
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/// Other bits are reserved.
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const HPET_CFG_WRITE_MASK: u64 = 0x003;
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/// bit 0, 7, and bits 16:31 are reserved.
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/// bit 4, 5, 15, and bits 32:64 are read-only.
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const HPET_TN_CFG_WRITE_MASK: u64 = 0x7f4e;
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/// Timer N Interrupt Type (bit 1)
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const HPET_TN_CFG_INT_TYPE_SHIFT: usize = 1;
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/// Timer N Interrupt Enable (bit 2)
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const HPET_TN_CFG_INT_ENABLE_SHIFT: usize = 2;
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/// Timer N Type (Periodic enabled or not, bit 3)
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const HPET_TN_CFG_PERIODIC_SHIFT: usize = 3;
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/// Timer N Periodic Interrupt Capable (support Periodic or not, bit 4)
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const HPET_TN_CFG_PERIODIC_CAP_SHIFT: usize = 4;
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/// Timer N Size (timer size is 64-bits or 32 bits, bit 5)
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const HPET_TN_CFG_SIZE_CAP_SHIFT: usize = 5;
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/// Timer N Value Set (bit 6)
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const HPET_TN_CFG_SETVAL_SHIFT: usize = 6;
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/// Timer N 32-bit Mode (bit 8)
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const HPET_TN_CFG_32BIT_SHIFT: usize = 8;
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/// Timer N Interrupt Rout (bits 9:13)
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const HPET_TN_CFG_INT_ROUTE_MASK: u64 = 0x3e00;
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const HPET_TN_CFG_INT_ROUTE_SHIFT: usize = 9;
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/// Timer N FSB Interrupt Enable (bit 14)
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const HPET_TN_CFG_FSB_ENABLE_SHIFT: usize = 14;
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/// Timer N FSB Interrupt Delivery (bit 15)
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const HPET_TN_CFG_FSB_CAP_SHIFT: usize = 15;
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/// Timer N Interrupt Routing Capability (bits 32:63)
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const HPET_TN_CFG_INT_ROUTE_CAP_SHIFT: usize = 32;
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#[derive(qemu_api_macros::TryInto)]
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#[repr(u64)]
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#[allow(non_camel_case_types)]
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/// Timer registers, masked by 0x18
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enum TimerRegister {
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/// Timer N Configuration and Capability Register
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CFG = 0,
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/// Timer N Comparator Value Register
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CMP = 8,
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/// Timer N FSB Interrupt Route Register
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ROUTE = 16,
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}
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#[derive(qemu_api_macros::TryInto)]
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#[repr(u64)]
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#[allow(non_camel_case_types)]
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/// Global registers
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enum GlobalRegister {
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/// General Capabilities and ID Register
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CAP = 0,
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/// General Configuration Register
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CFG = 0x10,
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/// General Interrupt Status Register
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INT_STATUS = 0x20,
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/// Main Counter Value Register
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COUNTER = 0xF0,
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}
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enum HPETRegister<'a> {
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/// Global register in the range from `0` to `0xff`
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Global(GlobalRegister),
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/// Register in the timer block `0x100`...`0x3ff`
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Timer(&'a BqlRefCell<HPETTimer>, TimerRegister),
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/// Invalid address
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#[allow(dead_code)]
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Unknown(hwaddr),
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}
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struct HPETAddrDecode<'a> {
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shift: u32,
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len: u32,
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reg: HPETRegister<'a>,
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}
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const fn hpet_next_wrap(cur_tick: u64) -> u64 {
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(cur_tick | 0xffffffff) + 1
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}
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const fn hpet_time_after(a: u64, b: u64) -> bool {
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((b - a) as i64) < 0
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}
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const fn ticks_to_ns(value: u64) -> u64 {
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value * HPET_CLK_PERIOD
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}
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const fn ns_to_ticks(value: u64) -> u64 {
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value / HPET_CLK_PERIOD
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}
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// Avoid touching the bits that cannot be written.
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const fn hpet_fixup_reg(new: u64, old: u64, mask: u64) -> u64 {
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(new & mask) | (old & !mask)
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}
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const fn activating_bit(old: u64, new: u64, shift: usize) -> bool {
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let mask: u64 = 1 << shift;
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(old & mask == 0) && (new & mask != 0)
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}
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const fn deactivating_bit(old: u64, new: u64, shift: usize) -> bool {
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let mask: u64 = 1 << shift;
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(old & mask != 0) && (new & mask == 0)
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}
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fn timer_handler(timer_cell: &BqlRefCell<HPETTimer>) {
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timer_cell.borrow_mut().callback()
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}
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/// HPET Timer Abstraction
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#[repr(C)]
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#[derive(Debug, qemu_api_macros::offsets)]
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pub struct HPETTimer {
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/// timer N index within the timer block (`HPETState`)
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#[doc(alias = "tn")]
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index: u8,
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qemu_timer: Timer,
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/// timer block abstraction containing this timer
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state: NonNull<HPETState>,
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// Memory-mapped, software visible timer registers
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/// Timer N Configuration and Capability Register
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config: u64,
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/// Timer N Comparator Value Register
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cmp: u64,
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/// Timer N FSB Interrupt Route Register
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fsb: u64,
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// Hidden register state
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/// comparator (extended to counter width)
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cmp64: u64,
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/// Last value written to comparator
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period: u64,
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/// timer pop will indicate wrap for one-shot 32-bit
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/// mode. Next pop will be actual timer expiration.
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wrap_flag: u8,
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/// last value armed, to avoid timer storms
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last: u64,
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}
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impl HPETTimer {
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fn init(&mut self, index: u8, state: &HPETState) {
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*self = HPETTimer {
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index,
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// SAFETY: the HPETTimer will only be used after the timer
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// is initialized below.
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qemu_timer: unsafe { Timer::new() },
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state: NonNull::new((state as *const HPETState).cast_mut()).unwrap(),
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config: 0,
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cmp: 0,
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fsb: 0,
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cmp64: 0,
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period: 0,
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wrap_flag: 0,
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last: 0,
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};
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// SAFETY: HPETTimer is only used as part of HPETState, which is
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// always pinned.
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let qemu_timer = unsafe { Pin::new_unchecked(&mut self.qemu_timer) };
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qemu_timer.init_full(
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None,
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CLOCK_VIRTUAL,
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Timer::NS,
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0,
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timer_handler,
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&state.timers[self.index as usize],
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)
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}
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fn get_state(&self) -> &HPETState {
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// SAFETY:
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// the pointer is convertible to a reference
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unsafe { self.state.as_ref() }
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}
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fn is_int_active(&self) -> bool {
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self.get_state().is_timer_int_active(self.index.into())
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}
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const fn is_fsb_route_enabled(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) != 0
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}
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const fn is_periodic(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_PERIODIC_SHIFT) != 0
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}
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const fn is_int_enabled(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_INT_ENABLE_SHIFT) != 0
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}
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const fn is_32bit_mod(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_32BIT_SHIFT) != 0
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}
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const fn is_valset_enabled(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_SETVAL_SHIFT) != 0
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}
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fn clear_valset(&mut self) {
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self.config &= !(1 << HPET_TN_CFG_SETVAL_SHIFT);
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}
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/// True if timer interrupt is level triggered; otherwise, edge triggered.
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const fn is_int_level_triggered(&self) -> bool {
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self.config & (1 << HPET_TN_CFG_INT_TYPE_SHIFT) != 0
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}
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/// calculate next value of the general counter that matches the
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/// target (either entirely, or the low 32-bit only depending on
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/// the timer mode).
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fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 {
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if self.is_32bit_mod() {
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let mut result: u64 = cur_tick.deposit(0, 32, target);
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if result < cur_tick {
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result += 0x100000000;
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}
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result
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} else {
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target
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}
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}
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const fn get_individual_route(&self) -> usize {
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((self.config & HPET_TN_CFG_INT_ROUTE_MASK) >> HPET_TN_CFG_INT_ROUTE_SHIFT) as usize
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}
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fn get_int_route(&self) -> usize {
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if self.index <= 1 && self.get_state().is_legacy_mode() {
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// If LegacyReplacement Route bit is set, HPET specification requires
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// timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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// timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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//
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// If the LegacyReplacement Route bit is set, the individual routing
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// bits for timers 0 and 1 (APIC or FSB) will have no impact.
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//
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// FIXME: Consider I/O APIC case.
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if self.index == 0 {
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0
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} else {
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RTC_ISA_IRQ
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}
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} else {
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// (If the LegacyReplacement Route bit is set) Timer 2-n will be
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// routed as per the routing in the timer n config registers.
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// ...
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// If the LegacyReplacement Route bit is not set, the individual
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// routing bits for each of the timers are used.
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self.get_individual_route()
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}
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}
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fn set_irq(&mut self, set: bool) {
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let route = self.get_int_route();
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if set && self.is_int_enabled() && self.get_state().is_hpet_enabled() {
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if self.is_fsb_route_enabled() {
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// SAFETY:
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// the parameters are valid.
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unsafe {
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address_space_stl_le(
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addr_of_mut!(address_space_memory),
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self.fsb >> 32, // Timer N FSB int addr
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self.fsb as u32, // Timer N FSB int value, truncate!
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MEMTXATTRS_UNSPECIFIED,
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null_mut(),
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);
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}
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} else if self.is_int_level_triggered() {
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self.get_state().irqs[route].raise();
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} else {
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self.get_state().irqs[route].pulse();
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}
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} else if !self.is_fsb_route_enabled() {
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self.get_state().irqs[route].lower();
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}
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}
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fn update_irq(&mut self, set: bool) {
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// If Timer N Interrupt Enable bit is 0, "the timer will
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// still operate and generate appropriate status bits, but
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// will not cause an interrupt"
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self.get_state()
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.update_int_status(self.index.into(), set && self.is_int_level_triggered());
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self.set_irq(set);
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}
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fn arm_timer(&mut self, tick: u64) {
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let mut ns = self.get_state().get_ns(tick);
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// Clamp period to reasonable min value (1 us)
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if self.is_periodic() && ns - self.last < 1000 {
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ns = self.last + 1000;
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}
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self.last = ns;
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self.qemu_timer.modify(self.last);
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}
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fn set_timer(&mut self) {
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let cur_tick: u64 = self.get_state().get_ticks();
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self.wrap_flag = 0;
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self.cmp64 = self.calculate_cmp64(cur_tick, self.cmp);
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if self.is_32bit_mod() {
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// HPET spec says in one-shot 32-bit mode, generate an interrupt when
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// counter wraps in addition to an interrupt with comparator match.
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if !self.is_periodic() && self.cmp64 > hpet_next_wrap(cur_tick) {
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self.wrap_flag = 1;
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self.arm_timer(hpet_next_wrap(cur_tick));
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return;
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}
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}
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self.arm_timer(self.cmp64);
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}
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fn del_timer(&mut self) {
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// Just remove the timer from the timer_list without destroying
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// this timer instance.
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self.qemu_timer.delete();
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if self.is_int_active() {
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// For level-triggered interrupt, this leaves interrupt status
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// register set but lowers irq.
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self.update_irq(true);
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}
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}
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/// Configuration and Capability Register
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fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) {
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// TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4)
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let old_val: u64 = self.config;
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let mut new_val: u64 = old_val.deposit(shift, len, val);
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new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
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// Switch level-type interrupt to edge-type.
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if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) {
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// Do this before changing timer.config; otherwise, if
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// HPET_TN_FSB is set, update_irq will not lower the qemu_irq.
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self.update_irq(false);
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}
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self.config = new_val;
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if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) && self.is_int_active() {
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self.update_irq(true);
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}
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if self.is_32bit_mod() {
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self.cmp = u64::from(self.cmp as u32); // truncate!
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self.period = u64::from(self.period as u32); // truncate!
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}
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if self.get_state().is_hpet_enabled() {
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self.set_timer();
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}
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}
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/// Comparator Value Register
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fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val: u64) {
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let mut length = len;
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let mut value = val;
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// TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4)
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if self.is_32bit_mod() {
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// High 32-bits are zero, leave them untouched.
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if shift != 0 {
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// TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp()
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return;
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}
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length = 64;
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value = u64::from(value as u32); // truncate!
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}
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if !self.is_periodic() || self.is_valset_enabled() {
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self.cmp = self.cmp.deposit(shift, length, value);
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}
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if self.is_periodic() {
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self.period = self.period.deposit(shift, length, value);
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}
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self.clear_valset();
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if self.get_state().is_hpet_enabled() {
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self.set_timer();
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}
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}
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/// FSB Interrupt Route Register
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fn set_tn_fsb_route_reg(&mut self, shift: u32, len: u32, val: u64) {
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self.fsb = self.fsb.deposit(shift, len, val);
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}
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fn reset(&mut self) {
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self.del_timer();
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self.cmp = u64::MAX; // Comparator Match Registers reset to all 1's.
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self.config = (1 << HPET_TN_CFG_PERIODIC_CAP_SHIFT) | (1 << HPET_TN_CFG_SIZE_CAP_SHIFT);
|
|
if self.get_state().has_msi_flag() {
|
|
self.config |= 1 << HPET_TN_CFG_FSB_CAP_SHIFT;
|
|
}
|
|
// advertise availability of ioapic int
|
|
self.config |=
|
|
(u64::from(self.get_state().int_route_cap)) << HPET_TN_CFG_INT_ROUTE_CAP_SHIFT;
|
|
self.period = 0;
|
|
self.wrap_flag = 0;
|
|
}
|
|
|
|
/// timer expiration callback
|
|
fn callback(&mut self) {
|
|
let period: u64 = self.period;
|
|
let cur_tick: u64 = self.get_state().get_ticks();
|
|
|
|
if self.is_periodic() && period != 0 {
|
|
while hpet_time_after(cur_tick, self.cmp64) {
|
|
self.cmp64 += period;
|
|
}
|
|
if self.is_32bit_mod() {
|
|
self.cmp = u64::from(self.cmp64 as u32); // truncate!
|
|
} else {
|
|
self.cmp = self.cmp64;
|
|
}
|
|
self.arm_timer(self.cmp64);
|
|
} else if self.wrap_flag != 0 {
|
|
self.wrap_flag = 0;
|
|
self.arm_timer(self.cmp64);
|
|
}
|
|
self.update_irq(true);
|
|
}
|
|
|
|
const fn read(&self, reg: TimerRegister) -> u64 {
|
|
use TimerRegister::*;
|
|
match reg {
|
|
CFG => self.config, // including interrupt capabilities
|
|
CMP => self.cmp, // comparator register
|
|
ROUTE => self.fsb,
|
|
}
|
|
}
|
|
|
|
fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) {
|
|
use TimerRegister::*;
|
|
match reg {
|
|
CFG => self.set_tn_cfg_reg(shift, len, value),
|
|
CMP => self.set_tn_cmp_reg(shift, len, value),
|
|
ROUTE => self.set_tn_fsb_route_reg(shift, len, value),
|
|
}
|
|
}
|
|
}
|
|
|
|
/// HPET Event Timer Block Abstraction
|
|
#[repr(C)]
|
|
#[derive(qemu_api_macros::Object, qemu_api_macros::offsets)]
|
|
pub struct HPETState {
|
|
parent_obj: ParentField<SysBusDevice>,
|
|
iomem: MemoryRegion,
|
|
|
|
// HPET block Registers: Memory-mapped, software visible registers
|
|
/// General Capabilities and ID Register
|
|
capability: BqlCell<u64>,
|
|
/// General Configuration Register
|
|
config: BqlCell<u64>,
|
|
/// General Interrupt Status Register
|
|
#[doc(alias = "isr")]
|
|
int_status: BqlCell<u64>,
|
|
/// Main Counter Value Register
|
|
#[doc(alias = "hpet_counter")]
|
|
counter: BqlCell<u64>,
|
|
|
|
// Internal state
|
|
/// Capabilities that QEMU HPET supports.
|
|
/// bit 0: MSI (or FSB) support.
|
|
flags: u32,
|
|
|
|
/// Offset of main counter relative to qemu clock.
|
|
hpet_offset: BqlCell<u64>,
|
|
hpet_offset_saved: bool,
|
|
|
|
irqs: [InterruptSource; HPET_NUM_IRQ_ROUTES],
|
|
rtc_irq_level: BqlCell<u32>,
|
|
pit_enabled: InterruptSource,
|
|
|
|
/// Interrupt Routing Capability.
|
|
/// This field indicates to which interrupts in the I/O (x) APIC
|
|
/// the timers' interrupt can be routed, and is encoded in the
|
|
/// bits 32:64 of timer N's config register:
|
|
#[doc(alias = "intcap")]
|
|
int_route_cap: u32,
|
|
|
|
/// HPET timer array managed by this timer block.
|
|
#[doc(alias = "timer")]
|
|
timers: [BqlRefCell<HPETTimer>; HPET_MAX_TIMERS as usize],
|
|
num_timers: BqlCell<u8>,
|
|
num_timers_save: BqlCell<u8>,
|
|
|
|
/// Instance id (HPET timer block ID).
|
|
hpet_id: BqlCell<usize>,
|
|
}
|
|
|
|
impl HPETState {
|
|
// Get num_timers with `usize` type, which is useful to play with array index.
|
|
fn get_num_timers(&self) -> usize {
|
|
self.num_timers.get().into()
|
|
}
|
|
|
|
const fn has_msi_flag(&self) -> bool {
|
|
self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) != 0
|
|
}
|
|
|
|
fn is_legacy_mode(&self) -> bool {
|
|
self.config.get() & (1 << HPET_CFG_LEG_RT_SHIFT) != 0
|
|
}
|
|
|
|
fn is_hpet_enabled(&self) -> bool {
|
|
self.config.get() & (1 << HPET_CFG_ENABLE_SHIFT) != 0
|
|
}
|
|
|
|
fn is_timer_int_active(&self, index: usize) -> bool {
|
|
self.int_status.get() & (1 << index) != 0
|
|
}
|
|
|
|
fn get_ticks(&self) -> u64 {
|
|
ns_to_ticks(CLOCK_VIRTUAL.get_ns() + self.hpet_offset.get())
|
|
}
|
|
|
|
fn get_ns(&self, tick: u64) -> u64 {
|
|
ticks_to_ns(tick) - self.hpet_offset.get()
|
|
}
|
|
|
|
fn handle_legacy_irq(&self, irq: u32, level: u32) {
|
|
if irq == HPET_LEGACY_PIT_INT {
|
|
if !self.is_legacy_mode() {
|
|
self.irqs[0].set(level != 0);
|
|
}
|
|
} else {
|
|
self.rtc_irq_level.set(level);
|
|
if !self.is_legacy_mode() {
|
|
self.irqs[RTC_ISA_IRQ].set(level != 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
fn init_timer(&self) {
|
|
for (index, timer) in self.timers.iter().enumerate() {
|
|
timer.borrow_mut().init(index.try_into().unwrap(), self);
|
|
}
|
|
}
|
|
|
|
fn update_int_status(&self, index: u32, level: bool) {
|
|
self.int_status
|
|
.set(self.int_status.get().deposit(index, 1, u64::from(level)));
|
|
}
|
|
|
|
/// General Configuration Register
|
|
fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) {
|
|
let old_val = self.config.get();
|
|
let mut new_val = old_val.deposit(shift, len, val);
|
|
|
|
new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
|
|
self.config.set(new_val);
|
|
|
|
if activating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) {
|
|
// Enable main counter and interrupt generation.
|
|
self.hpet_offset
|
|
.set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns());
|
|
|
|
for timer in self.timers.iter().take(self.get_num_timers()) {
|
|
let mut t = timer.borrow_mut();
|
|
|
|
if t.is_int_enabled() && t.is_int_active() {
|
|
t.update_irq(true);
|
|
}
|
|
t.set_timer();
|
|
}
|
|
} else if deactivating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) {
|
|
// Halt main counter and disable interrupt generation.
|
|
self.counter.set(self.get_ticks());
|
|
|
|
for timer in self.timers.iter().take(self.get_num_timers()) {
|
|
timer.borrow_mut().del_timer();
|
|
}
|
|
}
|
|
|
|
// i8254 and RTC output pins are disabled when HPET is in legacy mode
|
|
if activating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) {
|
|
self.pit_enabled.set(false);
|
|
self.irqs[0].lower();
|
|
self.irqs[RTC_ISA_IRQ].lower();
|
|
} else if deactivating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) {
|
|
// TODO: Add irq binding: qemu_irq_lower(s->irqs[0])
|
|
self.irqs[0].lower();
|
|
self.pit_enabled.set(true);
|
|
self.irqs[RTC_ISA_IRQ].set(self.rtc_irq_level.get() != 0);
|
|
}
|
|
}
|
|
|
|
/// General Interrupt Status Register: Read/Write Clear
|
|
fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) {
|
|
let new_val = val << shift;
|
|
let cleared = new_val & self.int_status.get();
|
|
|
|
for (index, timer) in self.timers.iter().take(self.get_num_timers()).enumerate() {
|
|
if cleared & (1 << index) != 0 {
|
|
timer.borrow_mut().update_irq(false);
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Main Counter Value Register
|
|
fn set_counter_reg(&self, shift: u32, len: u32, val: u64) {
|
|
if self.is_hpet_enabled() {
|
|
// TODO: Add trace point -
|
|
// trace_hpet_ram_write_counter_write_while_enabled()
|
|
//
|
|
// HPET spec says that writes to this register should only be
|
|
// done while the counter is halted. So this is an undefined
|
|
// behavior. There's no need to forbid it, but when HPET is
|
|
// enabled, the changed counter value will not affect the
|
|
// tick count (i.e., the previously calculated offset will
|
|
// not be changed as well).
|
|
}
|
|
self.counter
|
|
.set(self.counter.get().deposit(shift, len, val));
|
|
}
|
|
|
|
unsafe fn init(&mut self) {
|
|
static HPET_RAM_OPS: MemoryRegionOps<HPETState> =
|
|
MemoryRegionOpsBuilder::<HPETState>::new()
|
|
.read(&HPETState::read)
|
|
.write(&HPETState::write)
|
|
.native_endian()
|
|
.valid_sizes(4, 8)
|
|
.impl_sizes(4, 8)
|
|
.build();
|
|
|
|
// SAFETY:
|
|
// self and self.iomem are guaranteed to be valid at this point since callers
|
|
// must make sure the `self` reference is valid.
|
|
MemoryRegion::init_io(
|
|
unsafe { &mut *addr_of_mut!(self.iomem) },
|
|
addr_of_mut!(*self),
|
|
&HPET_RAM_OPS,
|
|
"hpet",
|
|
HPET_REG_SPACE_LEN,
|
|
);
|
|
}
|
|
|
|
fn post_init(&self) {
|
|
self.init_mmio(&self.iomem);
|
|
for irq in self.irqs.iter() {
|
|
self.init_irq(irq);
|
|
}
|
|
}
|
|
|
|
fn realize(&self) {
|
|
if self.int_route_cap == 0 {
|
|
// TODO: Add error binding: warn_report()
|
|
println!("Hpet's hpet-intcap property not initialized");
|
|
}
|
|
|
|
self.hpet_id.set(HPETFwConfig::assign_hpet_id());
|
|
|
|
if self.num_timers.get() < HPET_MIN_TIMERS {
|
|
self.num_timers.set(HPET_MIN_TIMERS);
|
|
} else if self.num_timers.get() > HPET_MAX_TIMERS {
|
|
self.num_timers.set(HPET_MAX_TIMERS);
|
|
}
|
|
|
|
self.init_timer();
|
|
// 64-bit General Capabilities and ID Register; LegacyReplacementRoute.
|
|
self.capability.set(
|
|
HPET_CAP_REV_ID_VALUE << HPET_CAP_REV_ID_SHIFT |
|
|
1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT |
|
|
1 << HPET_CAP_LEG_RT_CAP_SHIFT |
|
|
HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT |
|
|
((self.get_num_timers() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer
|
|
(HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT, // 10 ns
|
|
);
|
|
|
|
self.init_gpio_in(2, HPETState::handle_legacy_irq);
|
|
self.init_gpio_out(from_ref(&self.pit_enabled));
|
|
}
|
|
|
|
fn reset_hold(&self, _type: ResetType) {
|
|
for timer in self.timers.iter().take(self.get_num_timers()) {
|
|
timer.borrow_mut().reset();
|
|
}
|
|
|
|
self.counter.set(0);
|
|
self.config.set(0);
|
|
self.pit_enabled.set(true);
|
|
self.hpet_offset.set(0);
|
|
|
|
HPETFwConfig::update_hpet_cfg(
|
|
self.hpet_id.get(),
|
|
self.capability.get() as u32,
|
|
self.mmio_addr(0).unwrap(),
|
|
);
|
|
|
|
// to document that the RTC lowers its output on reset as well
|
|
self.rtc_irq_level.set(0);
|
|
}
|
|
|
|
fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode {
|
|
let shift = ((addr & 4) * 8) as u32;
|
|
let len = std::cmp::min(size * 8, 64 - shift);
|
|
|
|
addr &= !4;
|
|
let reg = if (0..=0xff).contains(&addr) {
|
|
GlobalRegister::try_from(addr).map(HPETRegister::Global)
|
|
} else {
|
|
let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
|
|
if timer_id <= self.get_num_timers() {
|
|
// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
|
|
TimerRegister::try_from(addr & 0x18)
|
|
.map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg))
|
|
} else {
|
|
// TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id)
|
|
Err(addr)
|
|
}
|
|
};
|
|
|
|
// reg is now a Result<HPETRegister, hwaddr>
|
|
// convert the Err case into HPETRegister as well
|
|
let reg = reg.unwrap_or_else(HPETRegister::Unknown);
|
|
HPETAddrDecode { shift, len, reg }
|
|
}
|
|
|
|
fn read(&self, addr: hwaddr, size: u32) -> u64 {
|
|
// TODO: Add trace point - trace_hpet_ram_read(addr)
|
|
let HPETAddrDecode { shift, reg, .. } = self.decode(addr, size);
|
|
|
|
use GlobalRegister::*;
|
|
use HPETRegister::*;
|
|
(match reg {
|
|
Timer(timer, tn_reg) => timer.borrow_mut().read(tn_reg),
|
|
Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */
|
|
Global(CFG) => self.config.get(),
|
|
Global(INT_STATUS) => self.int_status.get(),
|
|
Global(COUNTER) => {
|
|
// TODO: Add trace point
|
|
// trace_hpet_ram_read_reading_counter(addr & 4, cur_tick)
|
|
if self.is_hpet_enabled() {
|
|
self.get_ticks()
|
|
} else {
|
|
self.counter.get()
|
|
}
|
|
}
|
|
Unknown(_) => {
|
|
// TODO: Add trace point- trace_hpet_ram_read_invalid()
|
|
0
|
|
}
|
|
}) >> shift
|
|
}
|
|
|
|
fn write(&self, addr: hwaddr, value: u64, size: u32) {
|
|
let HPETAddrDecode { shift, len, reg } = self.decode(addr, size);
|
|
|
|
// TODO: Add trace point - trace_hpet_ram_write(addr, value)
|
|
use GlobalRegister::*;
|
|
use HPETRegister::*;
|
|
match reg {
|
|
Timer(timer, tn_reg) => timer.borrow_mut().write(tn_reg, value, shift, len),
|
|
Global(CAP) => {} // General Capabilities and ID Register: Read Only
|
|
Global(CFG) => self.set_cfg_reg(shift, len, value),
|
|
Global(INT_STATUS) => self.set_int_status_reg(shift, len, value),
|
|
Global(COUNTER) => self.set_counter_reg(shift, len, value),
|
|
Unknown(_) => {
|
|
// TODO: Add trace point - trace_hpet_ram_write_invalid()
|
|
}
|
|
}
|
|
}
|
|
|
|
fn pre_save(&self) -> i32 {
|
|
if self.is_hpet_enabled() {
|
|
self.counter.set(self.get_ticks());
|
|
}
|
|
|
|
/*
|
|
* The number of timers must match on source and destination, but it was
|
|
* also added to the migration stream. Check that it matches the value
|
|
* that was configured.
|
|
*/
|
|
self.num_timers_save.set(self.num_timers.get());
|
|
0
|
|
}
|
|
|
|
fn post_load(&self, _version_id: u8) -> i32 {
|
|
for timer in self.timers.iter().take(self.get_num_timers()) {
|
|
let mut t = timer.borrow_mut();
|
|
|
|
t.cmp64 = t.calculate_cmp64(t.get_state().counter.get(), t.cmp);
|
|
t.last = CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND;
|
|
}
|
|
|
|
// Recalculate the offset between the main counter and guest time
|
|
if !self.hpet_offset_saved {
|
|
self.hpet_offset
|
|
.set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns());
|
|
}
|
|
|
|
0
|
|
}
|
|
|
|
fn is_rtc_irq_level_needed(&self) -> bool {
|
|
self.rtc_irq_level.get() != 0
|
|
}
|
|
|
|
fn is_offset_needed(&self) -> bool {
|
|
self.is_hpet_enabled() && self.hpet_offset_saved
|
|
}
|
|
|
|
fn validate_num_timers(&self, _version_id: u8) -> bool {
|
|
self.num_timers.get() == self.num_timers_save.get()
|
|
}
|
|
}
|
|
|
|
qom_isa!(HPETState: SysBusDevice, DeviceState, Object);
|
|
|
|
unsafe impl ObjectType for HPETState {
|
|
// No need for HPETClass. Just like OBJECT_DECLARE_SIMPLE_TYPE in C.
|
|
type Class = <SysBusDevice as ObjectType>::Class;
|
|
const TYPE_NAME: &'static CStr = crate::TYPE_HPET;
|
|
}
|
|
|
|
impl ObjectImpl for HPETState {
|
|
type ParentType = SysBusDevice;
|
|
|
|
const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init);
|
|
const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init);
|
|
const CLASS_INIT: fn(&mut Self::Class) = Self::Class::class_init::<Self>;
|
|
}
|
|
|
|
// TODO: Make these properties user-configurable!
|
|
qemu_api::declare_properties! {
|
|
HPET_PROPERTIES,
|
|
qemu_api::define_property!(
|
|
c_str!("timers"),
|
|
HPETState,
|
|
num_timers,
|
|
unsafe { &qdev_prop_uint8 },
|
|
u8,
|
|
default = HPET_MIN_TIMERS
|
|
),
|
|
qemu_api::define_property!(
|
|
c_str!("msi"),
|
|
HPETState,
|
|
flags,
|
|
unsafe { &qdev_prop_bit },
|
|
u32,
|
|
bit = HPET_FLAG_MSI_SUPPORT_SHIFT as u8,
|
|
default = false,
|
|
),
|
|
qemu_api::define_property!(
|
|
c_str!("hpet-intcap"),
|
|
HPETState,
|
|
int_route_cap,
|
|
unsafe { &qdev_prop_uint32 },
|
|
u32,
|
|
default = 0
|
|
),
|
|
qemu_api::define_property!(
|
|
c_str!("hpet-offset-saved"),
|
|
HPETState,
|
|
hpet_offset_saved,
|
|
unsafe { &qdev_prop_bool },
|
|
bool,
|
|
default = true
|
|
),
|
|
}
|
|
|
|
unsafe extern "C" fn hpet_rtc_irq_level_needed(opaque: *mut c_void) -> bool {
|
|
// SAFETY:
|
|
// the pointer is convertible to a reference
|
|
let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() };
|
|
state.is_rtc_irq_level_needed()
|
|
}
|
|
|
|
unsafe extern "C" fn hpet_offset_needed(opaque: *mut c_void) -> bool {
|
|
// SAFETY:
|
|
// the pointer is convertible to a reference
|
|
let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() };
|
|
state.is_offset_needed()
|
|
}
|
|
|
|
unsafe extern "C" fn hpet_pre_save(opaque: *mut c_void) -> c_int {
|
|
// SAFETY:
|
|
// the pointer is convertible to a reference
|
|
let state: &mut HPETState =
|
|
unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() };
|
|
state.pre_save() as c_int
|
|
}
|
|
|
|
unsafe extern "C" fn hpet_post_load(opaque: *mut c_void, version_id: c_int) -> c_int {
|
|
// SAFETY:
|
|
// the pointer is convertible to a reference
|
|
let state: &mut HPETState =
|
|
unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() };
|
|
let version: u8 = version_id.try_into().unwrap();
|
|
state.post_load(version) as c_int
|
|
}
|
|
|
|
static VMSTATE_HPET_RTC_IRQ_LEVEL: VMStateDescription = VMStateDescription {
|
|
name: c_str!("hpet/rtc_irq_level").as_ptr(),
|
|
version_id: 1,
|
|
minimum_version_id: 1,
|
|
needed: Some(hpet_rtc_irq_level_needed),
|
|
fields: vmstate_fields! {
|
|
vmstate_of!(HPETState, rtc_irq_level),
|
|
},
|
|
..Zeroable::ZERO
|
|
};
|
|
|
|
static VMSTATE_HPET_OFFSET: VMStateDescription = VMStateDescription {
|
|
name: c_str!("hpet/offset").as_ptr(),
|
|
version_id: 1,
|
|
minimum_version_id: 1,
|
|
needed: Some(hpet_offset_needed),
|
|
fields: vmstate_fields! {
|
|
vmstate_of!(HPETState, hpet_offset),
|
|
},
|
|
..Zeroable::ZERO
|
|
};
|
|
|
|
static VMSTATE_HPET_TIMER: VMStateDescription = VMStateDescription {
|
|
name: c_str!("hpet_timer").as_ptr(),
|
|
version_id: 1,
|
|
minimum_version_id: 1,
|
|
fields: vmstate_fields! {
|
|
vmstate_of!(HPETTimer, index),
|
|
vmstate_of!(HPETTimer, config),
|
|
vmstate_of!(HPETTimer, cmp),
|
|
vmstate_of!(HPETTimer, fsb),
|
|
vmstate_of!(HPETTimer, period),
|
|
vmstate_of!(HPETTimer, wrap_flag),
|
|
vmstate_of!(HPETTimer, qemu_timer),
|
|
},
|
|
..Zeroable::ZERO
|
|
};
|
|
|
|
const VALIDATE_TIMERS_NAME: &CStr = c_str!("num_timers must match");
|
|
|
|
static VMSTATE_HPET: VMStateDescription = VMStateDescription {
|
|
name: c_str!("hpet").as_ptr(),
|
|
version_id: 2,
|
|
minimum_version_id: 1,
|
|
pre_save: Some(hpet_pre_save),
|
|
post_load: Some(hpet_post_load),
|
|
fields: vmstate_fields! {
|
|
vmstate_of!(HPETState, config),
|
|
vmstate_of!(HPETState, int_status),
|
|
vmstate_of!(HPETState, counter),
|
|
vmstate_of!(HPETState, num_timers_save).with_version_id(2),
|
|
vmstate_validate!(HPETState, VALIDATE_TIMERS_NAME, HPETState::validate_num_timers),
|
|
vmstate_struct!(HPETState, timers[0 .. num_timers], &VMSTATE_HPET_TIMER, BqlRefCell<HPETTimer>, HPETState::validate_num_timers).with_version_id(0),
|
|
},
|
|
subsections: vmstate_subsections! {
|
|
VMSTATE_HPET_RTC_IRQ_LEVEL,
|
|
VMSTATE_HPET_OFFSET,
|
|
},
|
|
..Zeroable::ZERO
|
|
};
|
|
|
|
impl DeviceImpl for HPETState {
|
|
fn properties() -> &'static [Property] {
|
|
&HPET_PROPERTIES
|
|
}
|
|
|
|
fn vmsd() -> Option<&'static VMStateDescription> {
|
|
Some(&VMSTATE_HPET)
|
|
}
|
|
|
|
const REALIZE: Option<fn(&Self)> = Some(Self::realize);
|
|
}
|
|
|
|
impl ResettablePhasesImpl for HPETState {
|
|
const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold);
|
|
}
|
|
|
|
impl SysBusDeviceImpl for HPETState {}
|