Max Filippov b7909d81f7 target-xtensa: implement MISC SR ... The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>		2012-12-08 18:48:26 +00:00
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core-dc232b	target-xtensa: add dc232b core	2011-10-16 10:40:02 +00:00
core-dc233c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf	target-xtensa: add fsf core	2011-10-16 10:40:16 +00:00
core-dc232b.c	target-xtensa: add license to core-dc232b.c	2012-04-15 17:43:28 +00:00
core-dc233c.c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf.c	target-xtensa: add license to core-fsf.c	2012-04-15 17:43:43 +00:00
cpu-qom.h	target-xtensa: QOM'ify CPU	2012-04-14 03:48:08 +04:00
cpu.c	target-xtensa: implement CACHEATTR SR	2012-12-08 18:48:26 +00:00
cpu.h	target-xtensa: implement MISC SR	2012-12-08 18:48:26 +00:00
helper.c	target-xtensa: implement CACHEATTR SR	2012-12-08 18:48:26 +00:00
helper.h	target-xtensa: implement ATOMCTL SR	2012-12-08 18:48:26 +00:00
machine.c	target-xtensa: add target stubs	2011-09-10 16:57:36 +00:00
Makefile.objs	target-xtensa: switch to AREG0-free mode	2012-06-10 20:09:22 +00:00
op_helper.c	target-xtensa: implement ATOMCTL SR	2012-12-08 18:48:26 +00:00
overlay_tool.h	target-xtensa: implement MISC SR	2012-12-08 18:48:26 +00:00
translate.c	target-xtensa: implement MISC SR	2012-12-08 18:48:26 +00:00
xtensa-semi.c	Rename target_phys_addr_t to hwaddr	2012-10-23 08:58:25 -05:00