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Found the following cpu feature bits missing from EPYC-Rome model. ibrs : Indirect Branch Restricted Speculation ssbd : Speculative Store Bypass Disable These new features will be added in EPYC-Rome-v2. The -cpu help output after the change. x86 EPYC-Rome (alias configured by machine type) x86 EPYC-Rome-v1 AMD EPYC-Rome Processor x86 EPYC-Rome-v2 AMD EPYC-Rome Processor Reported-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <161478622280.16275.6399866734509127420.stgit@bmoger-ubuntu> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> |
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