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4565917bb0
current code sets PCI_SEC_LATENCY_TIMER to RW, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, refer to the
[PCIe-to-PCI-PCI-X-Bridge] for requirements for this register.
also, fix typo in comment where it's made writeable - this typo
is likely what prevented us noticing we violate this requirement
in the 1st place.
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-Id: <de9d05366a70172e1789d10591dbe59e39c3849c.1693432039.git.mst@redhat.com>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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|---|---|---|
| .. | ||
| Kconfig | ||
| meson.build | ||
| msi.c | ||
| msix.c | ||
| pci-hmp-cmds.c | ||
| pci-internal.h | ||
| pci-qmp-cmds.c | ||
| pci-stub.c | ||
| pci.c | ||
| pci_bridge.c | ||
| pci_host.c | ||
| pcie.c | ||
| pcie_aer.c | ||
| pcie_doe.c | ||
| pcie_host.c | ||
| pcie_port.c | ||
| pcie_sriov.c | ||
| shpc.c | ||
| slotid_cap.c | ||
| trace-events | ||
| trace.h | ||