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This device models the RISC-V IOMMU as a sysbus device. The same design decisions taken in the riscv-iommu-pci device were kept, namely the existence of 4 vectors are available for each interrupt cause. The WSIs are emitted using the input of the s->notify() callback as a index to an IRQ list. The IRQ list starts at 'base_irq' and goes until base_irq + 3. This means that boards must have 4 contiguous IRQ lines available, starting from 'base_irq'. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
128 lines
3.9 KiB
C
128 lines
3.9 KiB
C
/*
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* QEMU emulation of an RISC-V IOMMU Platform Device
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/host-utils.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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#include "riscv-iommu.h"
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#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
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/* RISC-V IOMMU System Platform Device Emulation */
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struct RISCVIOMMUStateSys {
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SysBusDevice parent;
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uint64_t addr;
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uint32_t base_irq;
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DeviceState *irqchip;
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RISCVIOMMUState iommu;
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qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
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};
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static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
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unsigned vector)
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{
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RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
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uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
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/* We do not support MSIs yet */
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if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
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return;
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}
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qemu_irq_pulse(s->irqs[vector]);
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}
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static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
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{
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RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev);
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SysBusDevice *sysdev = SYS_BUS_DEVICE(s);
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PCIBus *pci_bus;
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qemu_irq irq;
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qdev_realize(DEVICE(&s->iommu), NULL, errp);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
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if (s->addr) {
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sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
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}
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pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL);
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if (pci_bus) {
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riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
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}
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s->iommu.notify = riscv_iommu_sysdev_notify;
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/* 4 IRQs are defined starting from s->base_irq */
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for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
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sysbus_init_irq(sysdev, &s->irqs[i]);
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irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
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sysbus_connect_irq(sysdev, i, irq);
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}
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}
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static void riscv_iommu_sys_init(Object *obj)
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{
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RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj);
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RISCVIOMMUState *iommu = &s->iommu;
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object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
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qdev_alias_all_properties(DEVICE(iommu), obj);
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iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
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riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
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}
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static Property riscv_iommu_sys_properties[] = {
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DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
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DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
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DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
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TYPE_DEVICE, DeviceState *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = riscv_iommu_sys_realize;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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device_class_set_props(dc, riscv_iommu_sys_properties);
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}
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static const TypeInfo riscv_iommu_sys = {
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.name = TYPE_RISCV_IOMMU_SYS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.class_init = riscv_iommu_sys_class_init,
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.instance_init = riscv_iommu_sys_init,
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.instance_size = sizeof(RISCVIOMMUStateSys),
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};
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static void riscv_iommu_register_sys(void)
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{
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type_register_static(&riscv_iommu_sys);
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}
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type_init(riscv_iommu_register_sys)
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