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8f90a54cfa
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector assignments specific to the Type 3 (T3) CXL device. The primary goal of this change is to encapsulate the MSIX vector uses that are unique to the T3 device within an enumeration, improving code readability and maintenance by avoiding magic numbers. This organizational change allows for more explicit references to each vector’s role, thereby reducing the potential for misconfiguration. It also modified `mailbox_reg_init_common` to accept the `msi_n` parameter, reflecting the new MSIX vector setup. This pertains to the T3 device privately; other endpoints should refrain from using it, despite its public accessibility to all of them. Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250203161908.145406-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Emulation of a CXL Switch Mailbox CCI PCIe function.
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*
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* Copyright (c) 2023 Huawei Technologies.
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*
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* From www.computeexpresslink.org
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* Compute Express Link (CXL) Specification revision 3.0 Version 1.0
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-bridge/cxl_upstream_port.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/qdev-properties.h"
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#include "hw/cxl/cxl.h"
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#define CXL_SWCCI_MSIX_MBOX 3
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static void cswmbcci_reset(DeviceState *dev)
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{
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CSWMBCCIDev *cswmb = CXL_SWITCH_MAILBOX_CCI(dev);
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cxl_device_register_init_swcci(cswmb, CXL_SWCCI_MSIX_MBOX);
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}
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static void cswbcci_realize(PCIDevice *pci_dev, Error **errp)
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{
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CSWMBCCIDev *cswmb = CXL_SWITCH_MAILBOX_CCI(pci_dev);
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CXLComponentState *cxl_cstate = &cswmb->cxl_cstate;
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CXLDeviceState *cxl_dstate = &cswmb->cxl_dstate;
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CXLDVSECRegisterLocator *regloc_dvsec;
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CXLUpstreamPort *usp;
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if (!cswmb->target) {
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error_setg(errp, "Target not set");
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return;
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}
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usp = CXL_USP(cswmb->target);
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pcie_endpoint_cap_init(pci_dev, 0x80);
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cxl_cstate->dvsec_offset = 0x100;
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cxl_cstate->pdev = pci_dev;
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cswmb->cci = &usp->swcci;
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cxl_device_register_block_init(OBJECT(pci_dev), cxl_dstate, cswmb->cci);
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pci_register_bar(pci_dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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&cxl_dstate->device_registers);
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regloc_dvsec = &(CXLDVSECRegisterLocator) {
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.rsvd = 0,
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.reg0_base_lo = RBI_CXL_DEVICE_REG | 0,
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.reg0_base_hi = 0,
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};
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cxl_component_create_dvsec(cxl_cstate, CXL3_SWITCH_MAILBOX_CCI,
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REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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REG_LOC_DVSEC_REVID, (uint8_t *)regloc_dvsec);
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cxl_initialize_mailbox_swcci(cswmb->cci, DEVICE(pci_dev),
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DEVICE(cswmb->target),
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CXL_MAILBOX_MAX_PAYLOAD_SIZE);
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}
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static void cswmbcci_exit(PCIDevice *pci_dev)
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{
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/* Nothing to do here yet */
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}
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static const Property cxl_switch_cci_props[] = {
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DEFINE_PROP_LINK("target", CSWMBCCIDev,
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target, TYPE_CXL_USP, PCIDevice *),
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};
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static void cswmbcci_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
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pc->realize = cswbcci_realize;
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pc->exit = cswmbcci_exit;
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/* Serial bus, CXL Switch CCI */
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pc->class_id = 0x0c0b;
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/*
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* Huawei Technologies
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* CXL Switch Mailbox CCI - DID assigned for emulation only.
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* No real hardware will ever use this ID.
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*/
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pc->vendor_id = 0x19e5;
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pc->device_id = 0xa123;
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pc->revision = 0;
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dc->desc = "CXL Switch Mailbox CCI";
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device_class_set_legacy_reset(dc, cswmbcci_reset);
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device_class_set_props(dc, cxl_switch_cci_props);
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}
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static const TypeInfo cswmbcci_info = {
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.name = TYPE_CXL_SWITCH_MAILBOX_CCI,
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.parent = TYPE_PCI_DEVICE,
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.class_init = cswmbcci_class_init,
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.instance_size = sizeof(CSWMBCCIDev),
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void cxl_switch_mailbox_cci_register(void)
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{
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type_register_static(&cswmbcci_info);
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}
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type_init(cxl_switch_mailbox_cci_register);
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