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This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
56 lines
769 B
Text
56 lines
769 B
Text
config HTIF
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bool
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config HART
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bool
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config IBEX
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bool
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config SIFIVE
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bool
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select MSI_NONBROKEN
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config SIFIVE_E
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bool
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select HART
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select SIFIVE
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select UNIMP
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config SIFIVE_U
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bool
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select CADENCE
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select HART
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select SIFIVE
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select UNIMP
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config SPIKE
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bool
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select HART
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select HTIF
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select SIFIVE
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config OPENTITAN
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bool
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select IBEX
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select HART
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select UNIMP
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config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply TEST_DEVICES
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select PCI
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select HART
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select SERIAL
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select GOLDFISH_RTC
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select VIRTIO_MMIO
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SIFIVE
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config MICROCHIP_PFSOC
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bool
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select HART
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select SIFIVE
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select UNIMP
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