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qemu/include/hw/cxl
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Hyeonggon Yoo bdd3159ad7 hw/cxl/device: read from register values in mdev_reg_read() 
In the current mdev_reg_read() implementation, it consistently returns
that the Media Status is Ready (01b). This was fine until commit
25a52959f9 ("hw/cxl: Add support for device sanitation") because the
media was presumed to be ready.

However, as per the CXL 3.0 spec "8.2.9.8.5.1 Sanitize (Opcode 4400h)",
during sanitation, the Media State should be set to Disabled (11b). The
mentioned commit correctly sets it to Disabled, but mdev_reg_read()
still returns Media Status as Ready.

To address this, update mdev_reg_read() to read register values instead
of returning dummy values.

Note that __toggle_media() managed to not only write something
that no one read, it did it to the wrong register storage and
so changed the reported mailbox size which was definitely not
the intent. That gets fixed as a side effect of allocating
separate state storage for this register.

Fixes: commit 25a52959f9 ("hw/cxl: Add support for device sanitation")
Signed-off-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
(cherry picked from commit f7509f462c)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-14 21:41:31 +03:00
..
cxl.h hw/cxl/mbox: Add Physical Switch Identify command. 2023-11-07 03:39:11 -05:00
cxl_cdat.h include/hw/pci: Break inclusion loop pci_bridge.h and cxl.h 2023-01-08 01:54:22 -05:00
cxl_component.h hw/cxl: Add a switch mailbox CCI function 2023-11-07 03:39:11 -05:00
cxl_device.h hw/cxl/device: read from register values in mdev_reg_read() 2024-02-14 21:41:31 +03:00
cxl_events.h hw/cxl: Line length reductions 2023-11-07 03:39:11 -05:00
cxl_host.h hw/cxl: Clean up includes 2023-02-08 07:16:23 +01:00
cxl_pci.h hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt 2023-11-07 03:39:11 -05:00